DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows:
Claims 1-12 are pending.
An action on the merits for claims 1-12 follows.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a) (d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
IDS
All references provided in the IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Package and Semiconductor Device Having Separated Bonding Wire and Lead.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, and 8 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Kodama (JP 2018-113284A). JP 2018-113284A was cited in the IDS dated 05/03/2024. The provided English translation is used for citation purposes.
Regarding Claim 1, Kodama teaches a package (110; Figs. 1a (plan-view), 1b (cross-sectional view), 2a (enlarged plan-view), 2b (perspective plan-view), 3a (cross-section of 2a), 3b (cross-section of 2b), Paragraph [0015]) comprising:
a base (10; Paragraph [0015]) having a mounting region (MR); Annotated Fig. 1b) on which a semiconductor chip (18; Figs. 1a, 1b, Paragraph [0012]) is to be mounted;
a frame (lower "body", (32); shown in Fig. 3a, Paragraph [0021]) provided on the base (10) so as to surround the mounting region (MR);
a first metal layer ("interconnection pattern," (36); labeled in Fig. 3a, Paragraph [0036]) provided on an upper surface of the frame (32), the first metal layer (36) including a first portion (1st Portion; Annotated Fig. 1b) to which a first bonding wire (leftmost "bonding wire," (24); Fig. 1a, 1b, omitted in Fig. 3a, Paragraph [0017]) electrically connecting the semiconductor chip (18) is to be bonded, a second portion (2nd Portion; Annotated Fig. 1b) farther from the mounting region (MR) than the first portion (1st Portion), and a first connecting portion (1st Connecting Portion; Annotated Fig. 1b) connecting the first portion (1st Portion) to the second portion (2nd Portion);
a first insulating layer (upper "body," (34); shown in Fig. 3a, Paragraph [0036]) provided on the first connecting portion (1st Connecting Portion) in contact with the first connecting portion (1st Connecting Portion), the first insulating layer (34) crossing (34 is seen to cross 36 in Fig. 3b) the first metal layer (36); and
a first lead ("one of the two leads," (40); Fig. 1b, Paragraph [0019]) bonded on the second portion (2nd portion).
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Regarding Claim 2, Kodama teaches the package (110) according to claim 1, wherein
each of the frame (32) and the first insulating layer (34) has ceramics as a main component ("The bodies 32 and 34 are formed of, for example, an insulator such as ceramic;" Paragraph [0021]).
Regarding Claim 4, Kodama teaches the package (110) according to claim 1, further comprising:
a second metal layer (second "wiring pattern," (36); Fig. 1b, Paragraph [0036]) provided on an upper surface of the frame (32), the second metal layer (second 36) including a third portion (1st Portion; Annotated Fig. 1b) to which a second bonding wire (rightmost "bonding wire," (24); Fig. 1a, 1b, omitted in Fig. 3a, Paragraph [0017]) electrically connecting the semiconductor chip (18) is to be bonded, a fourth portion (4th Portion; Annotated Fig. 1b) farther from the mounting region (MR) than the third portion (3rd Portion), and a second connecting portion (2nd Connecting Portion) connecting the third portion (3rd Portion) to the fourth portion (4th Portion);
a second insulating layer (upper "body," (34); shown in Fig. 3a, Paragraph [0036]) provided on the second connecting portion (2nd Connecting Portion) in contact with the second connecting portion (2nd Connecting Portion), the second insulating layer (34) crossing the second metal layer (36); and
a second lead ("one of the two leads," (40); Fig. 1b, Paragraph [0019]) bonded on the fourth portion (4th Portion). (Fig. 1b shows a second version of each of these elements on opposite sides of the mounting region and Fig. 3a shows an enhanced view of one of them.)
Regarding Claim 8, Kodama teaches a semiconductor device (“semiconductor device,” (100); Fig. 1b, Paragraph [0012]) comprising:
the package (110) according to claim 1; and
the semiconductor chip (18) mounted on the base (10).
Claims 5, 7, and 11 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Wakazono (US 20200251393 A1).
Regarding Claim 5, Wakazono teaches a package ("The semiconductor device includes […] a package;" Fig. 1 (cross-sectional view), 2 (plan view), 3 (circuit diagram), Paragraph [0017]) comprising:
a base ("base substrate," (10); Fig. 1, Paragraph [0017]) having a mounting region ("mounting area," (11); Paragraph [0018]) on which a semiconductor chip ("semiconductor element," (300); Paragraph [0018])) is to be mounted;
a frame ("dielectric layers," (110); Fig. 1, Paragraph [0021]) provided on the base (10) so as to surround the mounting region (11);
a first metal layer (layer including (121A, 122A); Fig. 1, Paragraph [0021]) provided on an upper surface of the frame (110), the first metal layer (121A, 122B) including a first portion ("element connector," (121A); Paragraph [0021]) to which a first bonding wire ("wiring part," (400A); Paragraph [0017) electrically connecting the semiconductor chip (300) is to be bonded, and a second portion ("frame connector," (122A); Paragraph [0021]) farther from the mounting region (11) than the first portion (121A) and separated from the first portion (121A) on an upper surface of the frame (110);
a first wiring ("electrode layer," (130) of left stack; Fig. 1, Paragraph [0021]) provided in the frame (110; Fig. 1) and electrically connecting the first portion (121A) to the second portion (122A); and
a first lead ("lead frame," (20A); Paragraph [0022]) bonded on the second portion (122A);
wherein the upper surface of the frame (110) is exposed from the first metal layer (121A, 122B; Fig. 1) so as to cross the first metal layer (121A, 122B; Fig. 2) in a region separating the first portion (121A) and the second portion (122B). (Frame 100 made up of dielectric layers 110 can be seen to cross between 121A and 122A in Fig. 2.)
Regarding Claim 7, Wakazono teaches the package ("The semiconductor device includes […] a package;" Fig. 1 (cross-sectional view), 2 (plan view), 3 (circuit diagram), Paragraph [0017]) according to claim 5, further comprising:
a second metal layer (layer including (121B, 122B); Fig. 1, Paragraph [0021])provided on the upper surface of the frame (110), the second metal layer (121B, 122B) including a third portion ("element connector," (121B); Paragraph [0021] to which a second bonding wire ("wiring part," (400B); Paragraph [0017]) electrically connecting the semiconductor chip (300) is to be bonded, and a fourth portion ("frame connector," (122B); Paragraph [0021]) farther from the mounting region (11) than the third portion (121B);
a second wiring ("electrode layer," (130) of right stack; Fig. 1, Paragraph [0021]) provided in the frame (110) and electrically connecting the third portion (121B) to the fourth portion (122B); and
a second lead ("lead frame," (20B); Paragraph [0022]) bonded on the fourth portion (122B);
wherein the upper surface of the frame (110) is exposed from the second metal layer (121B, 122B) so as to cross the second metal layer (121B, 122B) in a region separating the third portion (121B) and the fourth portion (122B). (Frame 100 made up of dielectric layers 110 can be seen to cross between 121B and 122B in Fig. 2.)
Regarding Claim 11, Wakazono teaches a semiconductor device (“semiconductor device,” (700); Fig. 1, Paragraph [0016]) comprising:
the package (Fig. 1) according to claim 5; and
the semiconductor chip (300) mounted on the base (10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kodama in view of Yamamoto et al. (US 6306526 B1), hereinafter Yamamoto.
Regarding Claim 3, Kodama teaches the package according to claim 1.
Kodama does not explicitly teach wherein a wettability of a surface of the first insulating layer with a solder is worse than a wettability of a surface of the first metal layer with the solder.
Yamamoto teaches a semiconductor package (Fig. 1b, Col. 2, Lines 45-50) wherein a wettability of a surface of the first insulating layer (uppermost portion of stepped “ceramic substrate,” (1); Col. 6, Lines 15-20) with a solder is worse than a wettability of a surface of the first metal layer (“metallized layer,” (7); Col. 6, Lines 25-30) with the solder (Yamamoto discloses that “the ceramic substrate itself is not solderable or wettable by molten solder” and that the plated “metallized layer has particularly high solderability (wettability by molten solder);” Col. 4, Lines 1-16. Therefore, the metal layer has a better solderability than the insulating layer).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Kodama with the teachings of Yamamoto such that the wettability of a surface of the first insulating layer with a solder is explicitly worse than a wettability of a surface of the first metal layer with the solder. This is because both devices use ceramic insulating materials for the insulating layer and metal for the metal layers and allowing the metal layer to be wettable has the benefit of it being able to be joined to other elements when forming a semiconductor device (Col. 4, Lines 1-16).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wakazono in view of Yamamoto et al. (US 6306526 B1), hereinafter Yamamoto.
Regarding Claim 6, Wakazono teaches the package according to claim 5.
Wakazono does not explicitly teach wherein a wettability of a surface of the frame with a solder is worse than a wettability of a surface of the first metal layer with the solder.
Yamamoto teaches a semiconductor package (Fig. 1b, Col. 2, Lines 45-50) wherein a wettability of a surface of the frame (“ceramic substrate,” (1); Col. 6, Lines 15-20) with a solder is worse than a wettability of a surface of the first metal layer (“metallized layer,” (7); Col. 6, Lines 25-30) with the solder (Yamamoto discloses that “the ceramic substrate itself is not solderable or wettable by molten solder” and that the plated “metallized layer has particularly high solderability (wettability by molten solder);” Col. 4, Lines 1-16. Therefore, the metal layer has a better solderability than the frame).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Wakazono with the teachings of Yamamoto such that the wettability of a surface of the frame with a solder is explicitly worse than a wettability of a surface of the first metal layer with the solder. This is because both devices use ceramic insulating materials for the frame and metal for the metal layers and allowing the metal layer to be wettable has the benefit of it being able to be joined to other elements when forming a semiconductor device (Col. 4, Lines 1-16).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kodama in view of Oya (US 20220165631 A1).
Regarding Claim 9, Kodama teaches the semiconductor device (100) according to claim 8.
Kodama does not explicitly teach a resin sealing material bonded to the upper surface of the frame and an upper surface of the first metal layer to seal the semiconductor chip.
Oyo teaches a semiconductor device (“semiconductor device,” (202); Fig. 1, Paragraph [0021]) comprising: a resin sealing material (“sealant,” (19) “is an epoxy-based resin”; Paragraph [0027]) bonded to the upper surface of the frame (“ceramic plate,” (13); Paragraph [0023]) and an upper surface of the first metal layer (“circuit pattern,” (12); Paragraph [0023]) to seal the semiconductor chip (“semiconductor element,” (10); Paragraph [0021]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kodama with the teaching of Oyo such that the device includes a resin sealing material to seal the semiconductor chip. Using a sealant to seal the interior of the device has the added benefit of securing insulation and preventing contamination of the interior of the device such as the semiconductor chip (Paragraph [0003]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kodama in view of Du et al. (US 20230197629 A1), hereinafter Du.
Regarding Claim 10, Kodama teaches a semiconductor device (100; Paragraph [0012]) comprising:
the package (110) according to claim 2;
the semiconductor chip (18) mounted on the base (10); and
a lid (“lid,” (13); Fig. 1b, Paragraph [0013]) bonded (Paragraph [0034]) to the upper surface of the frame (32) and an upper surface of the first insulating layer (34) to seal the semiconductor chip (18).
Kodama does not explicitly teach wherein the lid is bonded by using a resin adhesive.
Du teaches a semiconductor device (“electronic package,” (100); Figs. 1a (top-perspective view
1b (cross-sectional side-view), Paragraph [0031]) comprising:a lid (“lid,” (130); Paragraph [0038]) bonded to a frame (“ring structure,” (106); Paragraph [0032]) by using an adhesive resin (“such as by an adhesive material (e.g. […] resin;” Paragraph [0038]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Kodama with the teachings of Du such that the lid is bonded to the upper surface of the frame and an upper surface of the first insulating layer by using a resin adhesive. This is because using a resin material allows attachment between the lid and frame to be non-conductive. This has the added benefit of forming a seal ring that protects the internal elements of the semiconductor device (Paragraph [0038]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wakazono in view of Oya (US 20220165631 A1).
Regarding Claim 12, Wakazono teaches the semiconductor device (700) according to claim 11.
Wakazono does not explicitly teach a resin sealing material bonded to the upper surface of the frame and an upper surface of the first metal layer to seal the semiconductor chip. Oyo teaches a semiconductor device (“semiconductor device,” (202); Fig. 1, Paragraph [0021]) comprising: a resin sealing material (“sealant,” (19) “is an epoxy-based resin”; Paragraph [0027]) bonded to the upper surface of the frame (“ceramic plate,” (13); Paragraph [0023]) and an upper surface of the first metal layer (“circuit pattern,” (12); Paragraph [0023]) to seal the semiconductor chip (“semiconductor element,” (10); Paragraph [0021]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wakazono with the teaching of Oyo such that the device includes a resin sealing material to seal the semiconductor chip. Using a sealant to seal the interior of the device has the added benefit of securing insulation and preventing contamination of the interior of the device such as the semiconductor chip (Paragraph [0003]).
Conclusion
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/NOLAN GABRIEL STUESSY/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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