Prosecution Insights
Last updated: April 19, 2026
Application No. 18/654,527

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME

Non-Final OA §DP
Filed
May 03, 2024
Examiner
ALROBAIE, KHAMDAN N
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
89%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
545 granted / 635 resolved
+17.8% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
25 currently pending
Career history
660
Total Applications
across all art units

Statute-Specific Performance

§101
3.5%
-36.5% vs TC avg
§103
35.4%
-4.6% vs TC avg
§102
29.0%
-11.0% vs TC avg
§112
19.3%
-20.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 635 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,009,048. Although the claims at issue are not identical, they are not patentably distinct from each other because the current application claims the same limitations as the issued except the current application is broader than the issued patent. The current application recites similar limitations such as a first global power rail connected to a first power terminal, a second global power rail connected to a second power terminal, a third global power rail, a fourth global power rail, a power management circuit configured to receive a power down command from a controller, wherein the power management circuit is configured to connect the first global power rail to the third global power rail and the fourth global power rail in the normal mode of the high frequency operation, and wherein the power management circuit is configured to connect the first global power rail to the third global power rail and disconnect the first global power rail from the fourth global power rail in the standby mode of the high frequency operation. Allowable Subject Matter Claims 1-20 would be allowable if the double patenting rejection set forth in this Office action is overcame. The following is a statement of reasons for the indication of allowable subject matter: Kim et al. (US 2019/0027206 A1) memory device has a plurality of power rail. a first power rail for transmitting a high power voltage (Fig. 1, VDD2H), a second power rail for transmitting a low power voltage (Fig. 1, VDD2L), a third power rail for selectively receiving the high power voltage from the first power rail through a first dynamic voltage and frequency scaling (DVFS) switch and for selectively receiving the low power voltage from the second power rail through a second DVFS switch, a fourth power rail connected to a first power gating (PG) switch to selectively receive the high power voltage or the low power voltage from the third power rail, and a first circuit block connected to the fourth power rail to receive a power voltage to which the DVFS and PG are applied (Fig. 2). After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation: Regarding claim 1, a power management circuit configured to receive a power down command from a controller, and change a normal mode of a high frequency operation into a standby mode of the high frequency operation in response to the power down command, wherein the power management circuit is configured to connect the first global power rail to the third global power rail and the fourth global power rail in the normal mode of the high frequency operation, and wherein the power management circuit is configured to connect the first global power rail to the third global power rail and disconnect the first global power rail from the fourth global power rail in the standby mode of the high frequency operation. Regarding claim 8, a power management circuit configured to receive a power down command from a controller, and change a normal mode of a low frequency operation into a standby mode of the low frequency operation in response to the power down command related to the standby mode, wherein the power management circuit is configured to connect the second global power rail to the third global power rail and the fourth global power rail in the normal mode of the low frequency operation, and wherein the power management circuit is configured to connect the second global power rail to the third global power rail and disconnect the second global power rail from the fourth global power rail in the standby mode of the low frequency operation. Regarding claim 14, a fifth switch configured to connect the third global power rail to a plurality of first local power rails in response to a fifth power switching control signal; a sixth switch configured to connect the fourth global power rail to a plurality of second local power rails in response to a sixth power switching control signal; and a power management circuit configured to receive a power down command from a controller, change a normal mode into a standby mode in response to the power down command related to the standby mode, and generate the first power switching control signal to the sixth power switching control signal corresponding to the power down command. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

May 03, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603122
PARALLEL PIPE LATCH FOR MEMORY ACCESS OPERATIONS
2y 5m to grant Granted Apr 14, 2026
Patent 12603130
MEMORY AND READING, WRITING AND ERASING METHODS THEREOF
2y 5m to grant Granted Apr 14, 2026
Patent 12597466
SEMICONDUCTOR MEMORY DEVICES WITH DIFFERENTIAL THRESHOLD VOLTAGES
2y 5m to grant Granted Apr 07, 2026
Patent 12592280
RESISTIVE RANDOM ACCESS MEMORY AND MEMORY MINI-ARRAY THEREOF WITH IMPROVED RELIABILITY
2y 5m to grant Granted Mar 31, 2026
Patent 12586617
MEMORY MODULE AND SYSTEM SUPPORTING PARALLEL AND SERIAL ACCESS MODES
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
89%
With Interview (+2.8%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 635 resolved cases by this examiner. Grant probability derived from career allow rate.

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