DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 05/03/2024.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 05/03/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-6, and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2023/0095134)
Regarding claim 1, Chen discloses a method of manufacturing a semiconductor package, the method comprising:
bonding a first semiconductor chip 205 (see fig. 23) and a bridge structure 405 (para. 0022) onto a carrier structure 26 (or carrier structure 10);
bonding a second semiconductor chip 105a and a third semiconductor chip 105b onto the bridge structure 405, the second semiconductor chip 105a and the third semiconductor chip 105b being apart from each other in a horizontal direction; and
forming a plurality of connection bumps 30/32/34 (fig. 35) on the second semiconductor chip 105a and the third semiconductor chip 105b.
Regarding claim 2, Chen discloses the method of claim 1, wherein each of the bonding 454b/454d between the bridge structure 405 and the second semiconductor chip 105a and the bonding between the bridge structure 405 and the third semiconductor chip 105b is performed through a combination of dielectric-to-dielectric bonding and metal-to-metal bonding (hybrid bonding, see paras. 0067-0072). See fig. 23.
Regarding claim 3, Chen discloses the method of claim 1, wherein each of the bonding between the carrier structure 26 and the first semiconductor chip 205 and the bonding between the carrier structure 26 and the bridge structure 405 is performed through dielectric-to-dielectric bonding (via bonding layer 24). See fig. 23.
Regarding claim 4, Chen discloses:
a method of claim 1 comprising:
a method of manufacturing a semiconductor package, the method comprising:
bonding a first semiconductor chip 205 and a bridge structure 305 (para. 0022) onto a carrier structure 105a, 105b and/or 10 (see fig. 32);
bonding a second semiconductor chip 105c (fig. 33) and a third semiconductor chip 105d onto the bridge structure 305, the second semiconductor chip 105c and the third semiconductor chip 105d being apart from each other in a horizontal direction; and
forming a plurality of connection bumps 154 on the second semiconductor chip 105c and the third semiconductor chip 105d;
and (the method of claim 4):
further comprising, before the bonding of the second semiconductor chip 105c and the third semiconductor chip 105d:
forming a first preliminary gap-fill insulating layer 22 on the first semiconductor chip 205 and the bridge structure 305 (see fig. 32; see also figs. 14-16); and
forming a first gap-fill insulating layer 22 by planarizing the first preliminary gap-fill insulating layer 22 (figs. 15-16).
Regarding claim 5, Chen discloses the method of claim 4, wherein, after the bonding of the second semiconductor chip 105c and the third semiconductor chip 105d:
forming a second preliminary gap-fill insulating layer 40 (fig. 33) on the second semiconductor chip 105c and the third semiconductor chip 105d; and
forming a second gap-fill insulating layer 40 by planarizing the second preliminary gap-fill insulating layer 40 (figs. 33, 34).
Regarding claim 6, Chen discloses the method of claim 4, further comprising bonding the first gap-fill insulating layer 40 to the second semiconductor chip 105c and the third semiconductor chip 105d by dielectric-to-dielectric bonding. See figs. 32-34.
Regarding claim 8, Chen discloses the method of claim 1, wherein the bonding of the first semiconductor chip 205 and the bridge structure 405 comprises bonding at least one dummy structure 14, 22, and/or 20d (fig. 20) onto the carrier structure 10, 26.
Regarding claim 9, Chen discloses the method of claim 8, wherein the bonding of the at least one dummy structure 14/22/20d comprises bonding the at least one dummy structure between the carrier structure 10/26 and the second semiconductor chip 105a and between the carrier structure and the third semiconductor chip 105b. See figs. 17, 20.
Regarding claim 10, Chen discloses the method of claim 8, wherein the bonding between the at least one dummy structure 14/22/20a and the carrier structure 10, 26 is performed using dielectric-to-dielectric bonding. See figs. 17, 20.
Regarding claim 11, Chen discloses a method of manufacturing a semiconductor package, the method comprising:
bonding a bridge chip 305 and a plurality of dummy structures 14, 22, or 20d onto a carrier structure 10 or 26 (see figs. 17, 20);
connecting a first semiconductor chip 105a to a second semiconductor chip 105b through the bridge chip 305 by bonding the first semiconductor chip 105a and the second semiconductor chip 105b onto the bridge chip 305;
forming a cover insulating layer 28 (fig. 20) that covers the first semiconductor chip 105a and the second semiconductor chip 105b;
forming a plurality of connection vias 30 that pass through the cover insulating layer 28 to contact the first semiconductor chip 105a or the second semiconductor chip 105b; and
forming a plurality of connection bumps 32 on the cover insulating layer 28, the plurality of connection bumps 32 being in contact with the plurality of connection vias 30.
7. Claims 1-6, and 8-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. (US 2024/0079391)
Regarding claim 1, Hsu discloses a method of manufacturing a semiconductor package, the method comprising:
bonding a first semiconductor chip 50B and a bridge structure 50R onto a carrier structure 132 (see fig. 12);
bonding a second semiconductor chip 50A and a third semiconductor chip 50A onto the bridge structure 52R, the second semiconductor chip 50A and the third semiconductor chip 50A being apart from each other in a horizontal direction; and
forming a plurality of connection bumps 144 and/or 146 on the second semiconductor chip 50A and the third semiconductor chip 50A.
Regarding claim 2, Hsu discloses the method of claim 1, wherein each of the bonding between the bridge structure 50R and the second semiconductor chip 50A and the bonding between the bridge structure and the third semiconductor chip 50A is performed through a combination of dielectric-to-dielectric bonding and metal-to-metal bonding. See paras. 0038, 0041.
Regarding claim 3, Hsu discloses the method of claim 1, wherein each of the bonding between the carrier structure 132 and the first semiconductor chip 50A and the bonding between the carrier structure 132 and the bridge structure 50R is performed through dielectric-to-dielectric bonding. See fig. 12.
Regarding claim 4, Hsu discloses the method of claim 1, further comprising, before the bonding of the second semiconductor chip 50A and the third semiconductor chip 50A:
forming a first preliminary gap-fill insulating layer 126 on the first semiconductor chip 50B and the bridge structure 50R; and
forming a first gap-fill insulating layer 126 by planarizing the first preliminary gap-fill insulating layer. See paras. 0046-0048.
Regarding claim 5, Hsu discloses the method of claim 4, wherein, after the bonding of the second semiconductor chip 50A and the third semiconductor chip 50A:
forming a second preliminary gap-fill insulating layer 106 on the second semiconductor chip 50A and the third semiconductor chip 50A; and
forming a second gap-fill insulating layer 106 by planarizing the second preliminary gap-fill insulating layer. See paras. 0027-0031.
Regarding claim 6, Hsu discloses the method of claim 4, further comprising bonding the first gap-fill insulating layer 126 to the second semiconductor chip 50A and the third semiconductor chip 50A by dielectric-to-dielectric bonding. See fig. 12.
Regarding claim 8, Hsu discloses the method of claim 1, wherein the bonding of the first semiconductor chip 50B and the bridge structure 50R comprises bonding at least one dummy structure 120 onto the carrier structure 132. See fig. 12.
Regarding claim 9, Hsu discloses the method of claim 8, wherein the bonding of the at least one dummy structure 120 comprises bonding the at least one dummy structure 120 between the carrier structure 132 and the second semiconductor chip 50A and between the carrier structure 132 and the third semiconductor chip 50A. See fig. 12.
Regarding claim 10, Hsu discloses the method of claim 8, wherein the bonding between the at least one dummy structure 120 and the carrier structure 132 is performed using dielectric-to-dielectric bonding. See fig. 12.
Regarding claim 11, Hsu discloses a method of manufacturing a semiconductor package, the method comprising:
bonding a bridge chip 50R and a plurality of dummy structures 120 onto a carrier structure 132 (see fig. 12);
connecting a first semiconductor chip 50A to a second semiconductor chip 50A through the bridge chip 50R by bonding the first semiconductor chip 50A and the second semiconductor chip 50A onto the bridge chip 50R;
forming a cover insulating layer 142 that covers the first semiconductor chip 50A and the second semiconductor chip 50A;
forming a plurality of connection vias 144 that pass through the cover insulating layer 142 to contact the first semiconductor chip 50A or the second semiconductor chip 50A; and
forming a plurality of connection bumps 146 on the cover insulating layer 142, the plurality of connection bumps 146 being in contact with the plurality of connection vias 144.
Regarding claim 12, Hsu discloses the method of claim 11, wherein the plurality of dummy structures 120 are around the bridge chip 50R, and at least some of the plurality of dummy structures 120 overlap the first semiconductor chip 50A and the second semiconductor chip 50A, in a vertical direction, and contact the first semiconductor chip and the second semiconductor chip. See fig. 12.
Regarding claim 13, Hsu discloses the method of claim 11, further comprising forming a gap-fill insulating layer 126, 106 between the carrier structure 132 and the cover insulating layer 142, the gap-fill insulating layer 126, 106 surrounding the bridge chip 50R, the plurality of dummy structures 120, the first semiconductor chip 50A, and the second semiconductor chip 50A. See fig. 12.
Claim Rejections - 35 U.S.C. § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 7, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2024/0079391) in view of Mouli et al. (US 2007/0205792)
Regarding claim 7, Hsu discloses the method of claim 1, comprising all claimed limitations, as discussed above, except for further comprising forming a heat dissipation structure by removing a portion of the carrier structure.
Mouli discloses a method comprising forming a heat dissipation structure 22 & 24 & 58 by removing a portion (forming grooves 58) of a carrier structure 53 or 53 & 55. See fig. 6, and paras. 0045-0054.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Hsu to further forming a heat dissipation structure, as that taught by Mouli, in order to dissipate heat away from the package, thereby to increase the performance of the package.
Regarding claim 18, Hsu discloses a method of manufacturing a semiconductor package, the method comprising:
bonding a first semiconductor chip 50B, a bridge structure 50R, and a plurality of dummy structures 120 onto a carrier structure 132 (see fig. 12), the plurality of dummy structures 120 being around the first semiconductor chip 50B and the bridge structure 50R;
forming a first preliminary gap-fill insulating layer 126 that covers the first semiconductor chip 50B, the bridge structure 50R, and the plurality of dummy structures 120 (see paras. 0046-0048);
forming a first gap-fill insulating layer 126 that exposes the first semiconductor chip 50B, the bridge structure 50R, and the plurality of dummy structures 120, by planarizing the first preliminary gap-fill insulating layer 126;
bonding, onto the bridge structure 50R, a second semiconductor chip 50A and a third semiconductor chip 50A, such that the second semiconductor chip 50A is connected to the third semiconductor chip 50A via the bridge structure 50R;
forming a second preliminary gap-fill insulating layer 106 that covers the second semiconductor chip 50A and the third semiconductor chip 50A;
forming a second gap-fill insulating layer 106 that exposes the second semiconductor chip 50A and the third semiconductor chip 50A, by planarizing the second preliminary gap-fill insulating layer 106 (see paras. 0027-0031);
forming a cover insulating layer 142 on the second semiconductor chip 50A, the third semiconductor chip 50A, and the second gap-fill insulating layer 106;
forming a plurality of connection vias 144 that pass through the cover insulating layer 142 and are connected to the second semiconductor chip 50A or the third semiconductor chip 50A;
forming a plurality of connection bumps 146 on the cover insulating layer 142, the plurality of connection bumps 146 being respectively connected to the plurality of connection vias 144.
Hsu fails to disclose:
forming a heat dissipation structure by processing the carrier structure.
Mouli discloses:
a method comprising forming a heat dissipation structure 22 & 24 & 58 by removing a portion (forming grooves 58) of a carrier structure 53 or 53 & 55. See fig. 6, and paras. 0045-0054.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Hsu to further forming a heat dissipation structure, as that taught by Mouli, in order to dissipate heat away from the package, thereby to increase the performance of the package.
Regarding claim 19, Hsu/Mouli discloses the method of claim 18, wherein each of the bonding between the bridge structure 50R and the second semiconductor chip 50A and the bonding between the bridge structure 50R and the third semiconductor chip 50A is performed through a combination of dielectric-to-dielectric bonding and metal-to-metal bonding. See fig. 12, and paras. 0038-0041 of Hsu.
Regarding claim 20, Hsu/Mouli discloses the method of claim 18, wherein each of the bonding between the carrier structure 132 and the bridge structure 50R, the bonding between the carrier structure and the first semiconductor chip 50B, and the bonding between the carrier structure and the plurality of dummy structures 120 is performed through dielectric-to-dielectric bonding. See fig. 12.
Allowable Subject Matter
10. Claims 14-16, and 17 are allowable.
Claims 14-16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed method of manufacturing a semiconductor package (in addition to the other limitations in the claim) comprising:
Claims 14-16:
a heat dissipation bonding dielectric layer on the carrier substrate,
the bridge chip includes:
a first bonding dielectric layer facing the heat dissipation bonding dielectric layer;
wherein the bonding the bridge chip onto the carrier structure comprises bonding the carrier structure and the bridge chip together through dielectric-dielectric bonding between the bonding dielectric layer and the first bonding dielectric layer.
Claim 17:
wherein the carrier structure includes:
a heat dissipation bonding dielectric layer on the carrier substrate, each of the plurality of dummy structures includes:
a dummy-side bonding dielectric layer in contact with the heat dissipation bonding dielectric layer, on the heat dissipation bonding dielectric layer; and
a dummy substrate on the dummy-side bonding dielectric layer, and
the bonding the plurality of dummy structures comprises bonding the carrier structure to the plurality of dummy structures through dielectric-dielectric bonding between the heat dissipation bonding dielectric layer and the dummy-side bonding dielectric layer.
Conclusion
11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 June 5, 2026
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