DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/06/2024, 08/13/2024 and 02/18/2025 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,046,600. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,046,600 recites all of the limitations in claim 21 of the instant application.
Claim 22 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,046,600. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 3 of U.S. Patent No. 12,046,600 recites all of the limitations in claim 22 of the instant application.
Claim 23 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12,046,600. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 4 of U.S. Patent No. 12,046,600 recites all of the limitations in claim 23 of the instant application.
Claim 25 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 12,046,600. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 7 of U.S. Patent No. 12,046,600 recites all of the limitations in claim 25 of the instant application.
Claim 26 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 12,046,600. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of U.S. Patent No. 12,046,600 recites all of the limitations in claim 26 of the instant application. Claim 27 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. 12,046,600. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 19 of U.S. Patent No. 12,046,600 recites all of the limitations in claim 27 of the instant application.
Prior art of record
Re claim 21, Oh et al. (2013/0244392) teaches an integrated circuit structure (Figs. 25-27), comprising: an n-type MOS device (RG1), comprising: a first fin (F3) continuous with a substrate (100), the first fin having a channel region [53], wherein the first fin includes a first width (W1) (“lower width”) in a sub-channel region (“lower portion of fin”) below the channel region (“upper portion of fin”) and a second width (W2) (“upper width”) in the channel region (“upper portion of fin”), and wherein the channel region is narrower at a center of the channel region than at edges of the channel region (Fig. 27); and a first gate structure (143) over the channel region (Fig. 27) of the first fin (F3); and a p-type MOS device (RG2), comprising: a second fin (F1) continuous with the substrate (100), the second fin having a channel region (“upper portion of fin”), wherein the second fin (F1) includes a third width (W3) (“upper width”) in the channel region, and wherein W3 is greater than W2 (Fig. 27); and a second gate structure (143) over the channel region (“upper portion of fin”) of the second fin (F1). Oh does not explicitly teach wherein W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2, wherein the channel region has a height of at least 20 nm.
Re claim 27, Oh et al. (2013/0244392) teaches a method of fabricating an integrated circuit structure (Figs. 1-28), the method comprising: forming an n-type MOS device (RG1), the forming comprising: forming a first fin (F3) continuous with a substrate (100), the first fin having a channel region [53], wherein the first fin includes a first width (W1) (“lower width”) in a sub-channel region (“lower portion of fin”) below the channel region (“upper portion of fin”) and a second width (W2) (“upper width”) in the channel region (“upper portion of fin”), and forming a first gate structure (143) over the channel region of the first fin (F3); and forming a p-type MOS device (RG2), the forming comprising: forming a second fin (F1) continuous with the substrate (100), the second fin having a channel region (“upper portion of fin”), wherein the second fin (F1) includes a third width (W3) (“upper width”) in the channel region (Fig. 27), and wherein W3 is greater than W2 (Fig. 27); and forming a second gate structure (143) over the channel region of the second fin (F1). Oh does not explicitly teach wherein W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2, wherein the channel region has a height of at least 20 nm, and wherein the channel region is narrower at a center of the channel region than at edges of the channel region.
Re claim 33, Oh et al. (2013/0244392) teaches an integrated circuit structure (Figs. 25-27), comprising: an n-type MOS device (RG1), comprising: a first channel region [53] above a first sub-channel fin (“lower portion of fin”), the first sub-channel fin having a first width (W1) (“lower width”), and the first channel region having a second width (W2) (“upper width); and a first gate structure (143) over the first channel region (“upper portion of fin”); and a p-type MOS device (RG2), comprising: a second channel region [53] above a second sub-channel fin (“lower portion of fin”), wherein the second channel region has a third width (W3) (“upper width”), and wherein W3 is greater than W2 (Fig. 27); and a second gate structure (143) over the second channel region [53]. Oh does not explicitly teach wherein W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2, and wherein the first channel region is narrower at a center of the first channel region than at edges of the first channel region.
Re claim 39, Oh et al. (2013/0244392) teaches a method of fabricating an integrated circuit structure (Figs. 1-28), the method comprising: forming an n-type MOS device (RG1), the forming comprising: forming a first channel region [53] above a first sub-channel fin (“lower portion of fin”), the first sub-channel fin having a first width (W1) (“lower width”), and the first channel region (“upper fin portion”) having a second width (W2) (“upper width”); and forming a first gate structure (143) over the first channel region [53]; and forming a p-type MOS device (RG2), the forming comprising: forming a second channel region [53] above a second sub-channel fin (“lower fin portion”), wherein the second channel region has a third width (W3) (“upper width”), and wherein W3 is greater than W2 (Fig. 27); and forming a second gate structure (143) over the second channel region [53].
Oh does not explicitly teach wherein W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2, and wherein the first channel region is narrower at a center of the first channel region than at edges of the first channel region.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not anticipate or make obvious the device of claim 21, including each of the limitations and specifically wherein W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2, wherein the channel region has a height of at least 20 nm, for the same reasons as mentioned for claim 21 in the prior art of record above. The prior art of record does not anticipate or make obvious the method of claim 27, including each of the limitations and specifically wherein W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2, wherein the channel region has a height of at least 20 nm, and wherein the channel region is narrower at a center of the channel region than at edges of the channel region, for the same reasons as mentioned for claim 27 in the prior art of record above. The prior art of record does not anticipate or make obvious the device of claim 33, including each of the limitations and specifically wherein W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2, and wherein the first channel region is narrower at a center of the first channel region than at edges of the first channel region, for the same reasons as mentioned for claim 33 in the prior art of record above.
The prior art of record does not anticipate or make obvious the method of claim 39, including each of the limitations and specifically wherein W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2, and wherein the first channel region is narrower at a center of the first channel region than at edges of the first channel region, for the same reasons as mentioned for claim 39 in the prior art of record above.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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