Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 9, 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 2, 9,16 line 24 recites “obtain two or more measurements of one or delays to a clock of the one or more integrated circuits, each measurement representing a delay that can be applied without causing errors”, the terminologies are unclear and the use of this phrase which renders the claim indefinite because it is not clear with the terminology “one or delays to a clock of the one or more integrated circuits, each measurement representing a delay ”.
Specifically, claim 2 recites the limitations:
i)“obtain two or more measurements of one or delays ..” , it is not clear how two measurements are obtained from one delays to a clock and whether it is : obtain one or more measurements of delays to a clock ; or obtain two or more measurements of delays to a clock.
ii) “ each measurement representing a delay”, it is not clear whether each measurement representing a delay to the clock or another delay not representing a delay to the clock.
Examiner interprets as “obtain two or more measurements of delays to a clock of the one or more integrated circuits, each measurement representing a delay to the clock..”, that can be applied without causing errors” as disclosed in the specification document [ 0062, 0064 , 0065].
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Regarding Claim(s) 1, 8, 15 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Venumuddala et.al. (U.S Patent Application Publication 2015/0241942; hereinafter “Venumuddla”].
Regarding Claim 1, Venumuddala discloses , A One or more processors, comprising:
circuitry to:[ “FIG. 1 illustrates a system on a chip (SOC) 100 that includes a hardware-based voltage and frequency scaling system 104 for power optimization. The hardware-based voltage and frequency scaling system 104 may use processor throughput information in, for example, an adaptive throughput feedback process for power optimization”, 0018; Fig.1];
measure a throughput of one or more integrated circuits during execution of a user program[ “the voltage and frequency scaling systems disclosed herein operate with regard to frames (periods of time) such that a "current workload" for a given frame relates to the number of processor-executing-instructions clock cycles as compared to the total number of clock cycles in that frame. A related concept to workload is processor "throughput," which also has a generally-understood meaning in the processor arts and relates to the data output or analogous output from the computer. For example, a graphics processor may have to process a certain number of video frames per second (e.g., 30 frames per second or whatever is required under the relevant video standard). Similarly, a processor interfacing with a database may need to have the throughput to satisfy a certain number of database queries per second. This processing of data is quantified as necessary in the present disclosure so that a current throughput may be determined in a given frame..”, 0013; 0016; ( i.e measuring throughout based on the frames executed during video processing sessions/ programs); “..With regard to each frame, translators 202 and 204 may maintain counters to translate the workload and throughput signals as received from processor 102 (illustrated as feedback 106 in FIG. 1) at the processor clocking rate to the frame rate. In any given frame, workload translator module 202 receives the workload signal from the processor and determines a current workload (CW) accordingly for that frame. As used herein, a "frame" without further limitation refers to the current frame. In that regard, throughput translator module 204 receives the throughput signal from the processor and determines a current throughput (CT) for the frame.”,0020;” throughput tracker module 208 calculates an average throughput (Ac) based upon the current throughput CT from throughput translator module 204. ..”, 0022; ” For example, a current workload CW and throughput CT pair may be received and processed such that the current workload CW is assigned to a workload bin and the current throughput CT is averaged into a current profiled throughput value that is stored in association with that workload bin in LUT 314.., a dynamically updated profiled throughput that corresponds to each workload bin (sometimes referred to herein as a workload range) may be stored and continuously updated in the lookup table.”, 0036; (i.e. measuring the current throughput during execution of frames and obtaining an average throughput corresponds to the measured throughput)]; and
dynamically adjust an operating frequency of the one or more integrated circuits based, at least in part, on a difference between the measured throughput and a prior measured throughput. [ “With regard to each frame, the voltage and frequency scaling system need only receive a workload (WL) and throughput (THPT) feedback from the processor… This scaling occurs with regard to a finite set of possible voltage and frequency values for the processor that are denoted herein as performance settings. Each performance setting thus corresponds to a particular supply voltage and clock frequency assignment for the processor.”, 0006; 0040; “:with regard to a current frame in a series of frames, operating a processor in the current frame according to a current performance setting selected from a set of performance settings, wherein each performance setting equals a corresponding power supply voltage and clock frequency setting for the processor.”, 0056; “The desired throughput R may be provided to system 104 and stored (e.g., in control and status registers in the module) or the desired throughput R may be determined by the system. In scenarios where the desired throughput is not known prior to task execution, the throughput may be monitored for a brief period of time (e.g., an adjustable time period) while the system is running at a maximum performance level. The average throughput during this time period may be measured and used as the desired throughput for upcoming DVFS frames.”, 0044; ( i.e the desired throughput is measured prior to task execution corresponds to the prior throughput); “If the average throughput Ac is less than or equal to the desired throughput R, module 210 may proceed to block 326. At block 326, an incrementally increased performance setting (PERF++) may be determined and mapped to a corresponding workload bin, and hence, a corresponding predicted throughput A..”, 0045; “If, at block 318, the current average throughput Ac is greater than the desired throughput R, module 210 may instead proceed to block 320…”, 0051; “..At block 324, system 104 may command the processor to decrease the current performance setting”, 0053; “In this way, the operations performed in connection with blocks 320, 322, and 324 may maintain or decrease the performance setting of processor 102 as appropriate to conserve power when the current average throughput is higher than the desired throughput.”, 0054; ( i.e determining a difference between the measured throughput with the desired (prior) throughput and adjusting the performance setting( voltage and clock frequency). Hence dynamically adjusting/ scaling the frequency based on the difference with the throughput)].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 7, 10, 11, 14, 17, 18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Venumuddala in view of Frid et.al. (U.S Patent Application Publication 2009/0204830; hereinafter “Frid”; Reference cited as prior art in previous office action)
1
Regarding claims 3, 10, 17, Venumuddala teaches the limitations as laid out in claims 1, 8, 15.
However, Venumuddala does not expressly disclose , wherein the one or more circuits are to compare two or more sets of data collected during performance of two or more applications, the two or more applications comprising a reference application corresponding to a reference frequency and a user application corresponding to a user frequency.
In the same field of endeavor ( e.g. a central processing unit (CPU, e.g., a microprocessor) identifies a type of task to be performed and a device to perform that task. Based on the type of task and also on the device identified, the CPU selects an initial (or baseline) frequency for a clock signal to be used by the device(s) to perform the task and scaling the frequency from the baseline based on the workload), Frid teaches,
wherein the one or more circuits are to compare two or more sets of data collected during performance of two or more applications, the two or more applications comprising a reference application corresponding to a reference frequency and a user application corresponding to a user frequency [ “ the CPU 102 implements a power management technique that may be referred to as dynamic frequency scaling (DFS). In general, DFS provides a mechanism for adjusting the frequencies of the clock signals used by the devices in the system 100. “, 0027; “ an initial (baseline) frequency is specified by the CPU 102, depending on the type of task or use case to be executed by the device 214 at any time. The baseline frequency is a function of task and which device is used for the task. If multiple devices are performing the same task, a different baseline frequency may be specified for each device.”, 0035; “ If the baseline frequency needs to be increased because the performance level associated with the baseline frequency is not adequate to perform the task in a manner required or desired, the CPU 102 can be awakened using an interrupt that is issued by the device 214 in response to a triggering event. Triggering events are generally categorized herein as "starvation" triggers and "busyness" triggers. Triggering events may also be referred to as real-time events.”, 0038; “In response to the interrupt, the CPU 102 awakens so that it can specify a new (higher) frequency for the clock generator 218, thereby increasing the performance of the device 214. ..”, 0040; “ busyness trigger is a predicted change in workload for the device 214. For example, the device 214 may be executing a particular task when the device driver identifies a pending task that is more computationally intensive then the currently executing task. In one embodiment, the device 214 sends an interrupt to the CPU 102 if the device predicts an increase in its workload. In response to the interrupt, the CPU 102 awakens so that it can specify a new (higher) frequency for the clock generator 218.”, 0041; ( i.e. the CPU compares the performance of the tasks executing on the device based on whether the new workload is computationally intensive or not. Task or workload at the baseline frequency corresponds to reference workload at reference frequency and the new frequency corresponding to the change in workload / task corresponds to a user application corresponding to a user frequency)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Venumuddala with Frid. Frid’s teaching of setting a baseline frequency based on the device and type of workload and a central processing unit (CPU) entering a reduced power mode after the setting will substantially improve Venumuddala’s system to reduce power consumption by preventing “the CPU to run continuously at full power--once the CPU selects a device and a baseline frequency, it can be powered down or turned off until it is needed. Second, the frequency of the clock signal used by the device is adjusted up and down depending on workload-- By intelligently selecting an appropriate baseline frequency and then adjusting it as needed, and by selectively running the CPU in the manner just described, a net savings in power is realized”[ 0009].
Regarding claims 4, 11, 18, Venumuddala discloses, the measured throughput indicates a change of frequency of a processing unit [0013;0016; 0019; 0020; 0022; 0036; Fig.2].
However, Venumuddala does not expressly discloses change of design frequency.
Frid teaches design frequency [ “ an initial (baseline) frequency is specified by the CPU 102, depending on the type of task or use case to be executed by the device 214 at any time. The baseline frequency is a function of task and which device is used for the task. If multiple devices are performing the same task, a different baseline frequency may be specified for each device.”, 0035; ( i.e is the baseline frequency corresponds to the design frequency)].
Regarding claims 7, 14, 20, Frid teaches wherein the one or more circuits are to select different frequencies of a processing unit for different applications [0027; 0035; 0040-0041; Fig.4,5].
Claims 5, 6, 12, 13, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Venumuddala in view of Chawla et.al. (U.S Patent Application Publication 2011/0068858; hereinafter “Chawla”; Reference cited as prior art in previous office action)
Regarding claims 5, 12, 19, Venumuddala discloses the one or more circuits , measured throughput [0013;0016; 0019; 0020; 0022; 0036; Fig.2].
However, Venumuddala does not expressly disclose wherein the one or more circuits are to use one or more critical path monitors to obtain data indicative of the measured throughput.
In the same field of endeavor ( e.g. maximizing energy efficiency for a given throughput of a system on chip (SoC) circuit operation by dynamically operating the SoC circuit at the margins of acceptable voltage and/or frequency), Chawla teaches,
wherein the one or more circuits are to use one or more critical path monitors to obtain data indicative of the measured throughput [ “The actual or typical operating conditions for the SoC circuit are rarely at or even near such worst case conditions, and thus the SoC circuit most often operates with more than necessary safety margins. This is undesirable to some degree as it results in inefficiency. However, it is known to try and recover these available margins by operating the SoC circuit with reduced voltage (lower power) and/or increased frequency (increased throughput) for a given operating condition. …”, 0004; “ the controller 118 may alternatively, or additionally, respond to the margin signal from the critical path replica circuit 120 by adjusting the frequency of SoC circuit digital domain 112 operation (for example, by increasing clock frequency output from an adaptive clock generator 126) so to recover available operating system margin…”, 0029; “The SoC circuit 100 includes a number of in situ fail-safe timing sensors 122 associated at the very least with the digital domain 112… Analogously, as shown in FIG. 3 for an adaptive frequency scaling (AFS) circuit 124 solution, the controller 118 may alternatively, or additionally, respond to the sensor 122 input by adjusting the frequency of SoC circuit digital domain 112 operation “, 0030; “Each fail-safe timing sensor 122 is a critical path end point monitor circuit which can be used to forecast failure (see, FIG. 5 and discussion herein)….”, 0032; “The information provided by the fail-safe timing sensors 122 can be used by the controller 118 to implement a fault prevention operating mode. In this configuration, any indication from an included sensor 122 of an actual or potential violation of safe timing margin on the SoC circuit digital domain 112 can over-ride (or supplement) the margin signal information supplied by the critical path replica circuit 120 in the controller 118 and prevent further changes from being made, or reverse previously made changes, as to voltage (regulator 116) or clock frequency (generator 126). In this way, a fault-prevention mode of operation is provided which nonetheless maximizes energy efficiency at a given throughput.”:, 0034-0035; ( i.e the data obtained from the fail-safe timing sensors/ critical path monitors is indicative to increase the throughput)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Venumuddala with Chawla. Chawla’s teaching of implementing fail-safe timing sensors within and across the SoC circuit 100 digital domain where each of them is a critical path end point monitor circuit will substantially improve Venumuddala’s system to prevent any failure occurring as a result of adaptive frequency scaling by forecasting violation of safe timing margin on the SoC circuit and providing the information to the controller to implement a fault prevention operating mode[0034].
Regarding claims 6, 13, Chawla teaches wherein the measurement is performed in one or more critical paths [ 0031-0032; 0035; Fig.2] .
Allowable Subject Matter
Claims 2, 9, 16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, 15 have been considered but are moot because the arguments do not apply to Venumuddala reference being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kothiwale et al., U.S Patent Application Publication 2021/0072814, teaches a method and an apparatus for operating a processor in an electronic device. The method includes identifying an average throughput for a first set of subframes, predicting a load of the processor for a second set of subframes based on the identified average throughput, determining an operating frequency of the processor for the second set of subframes based on the predicted load, and operating the processor on the determined operating frequency for the second set of subframes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAYATHRI SAMPATH/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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