Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-10, and 13-20 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Duan et al. (Pub. No. US 20240030065 A1), hereinafter referred to as Duan.
Regarding claim 1, Duan teaches a package comprising: a first integrated device; a second integrated device (Fig. 15, panel 1500, integrated circuit die 1508, integrated circuit dies 1504a-1504d; ¶127-131); and a package interposer coupled to the first integrated device and the second integrated device, the package interposer comprising: a first metallization portion; a second metallization portion; a first encapsulation layer coupled to the first metallization portion and the second metallization portion (Fig. 15, panel substrate 1501, stacked dielectric layers 1522, stacked dielectric layers 1524, glass core 1551; ¶127-131); and a passive device located at least partially in the first encapsulation layer, wherein the first encapsulation layer and the passive device are located between the first metallization portion and the second metallization portion (Fig. 15, local interconnect component 1534, glass core 1551; ¶127-131).
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Regarding claim 2, Duan further teaches the passive device comprising a trench capacitor device (Figs. 4B & 15, local interconnect component 1534, local interconnect component 435, trench capacitor 456; ¶80-81, 127-131).
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Regarding claim 3, Duan further teaches the trench capacitor device comprising at least one through substrate via (Fig. 4B, via 452; ¶80-81).
Regarding claim 6, Duan further teaches the first integrated device being coupled to the package interposer through a first plurality of solder interconnects; and wherein the second integrated device is coupled to the package interposer through a second plurality of solder interconnects (Fig. 15, solder balls 1538; ¶127-131).
Regarding claim 7, Duan further teaches a second encapsulation layer coupled to the package interposer, the first integrated device and the second integrated device (Fig. 14, encapsulant 1498; ¶122-131).
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Regarding claim 8, Duan further teaches the package interposer further comprising a bridge located at least partially in the first encapsulation layer (Fig. 4A, local interconnect component 434, glass sheet 450; ¶74-79).
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Regarding claim 9, Duan further teaches the first integrated device configured to be electrically coupled to the second integrated device through at least the first metallization portion and the bridge (Fig. 15, integrated circuit die 1508, integrated circuit dies 1504a-1504d, vias 1528b, local interconnect component 1534, stacked dielectric layers 1522; ¶127-131).
Regarding claim 10, Duan further teaches the first integrated device is configured to be electrically coupled to the second integrated device through at least the second metallization portion and the bridge (Fig. 15, integrated circuit die 1508, integrated circuit dies 1504a-1504d, local interconnect component 1534, stacked dielectric layers 1524, conductive traces 1528a, vias 1528b, conductive traces 1530a, vias 1530b, through-glass vias (TGVs) 1552; ¶127-131).
Regarding claim 13, Duan further teaches a plurality of post interconnects located at least partially in the first encapsulation layer, wherein the plurality of post interconnects is coupled to the first metallization portion and the second metallization portion (Fig. 15, through-glass vias (TGVs) 1552; ¶127-131).
Regarding claim 14, Duan further teaches the first metallization portion comprising: at least one first dielectric layer; and a first plurality of metallization interconnects, and wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects (Fig. 15, conductive traces 1528a, vias 1528b, stacked dielectric layers 1522a-1522d, conductive traces 1530a, vias 1530b, stacked dielectric layers 1524a & 1524b; ¶127-131).
Regarding claim 15, Duan further teaches the first integrated device including a system on chip, and wherein the second integrated device includes memory device (Fig. 15, integrated circuit die 1508, integrated circuit dies 1504a-1504d; ¶44-45, 127-131).
Regarding claim 16, Duan teaches a device comprising: a package comprising: a first integrated device; a second integrated device (Figs. 15 & 30, panel 1500, integrated circuit die 1508, integrated circuit dies 1504a-1504d, electrical device 3000; ¶127-131, 237-251); and a package interposer coupled to the first integrated device and the second integrated device, the package interposer comprising: a first metallization portion; a second metallization portion; a first encapsulation layer coupled to the first metallization portion and the second metallization portion (Fig. 15, panel substrate 1501, stacked dielectric layers 1522, stacked dielectric layers 1524, glass core 1551; ¶127-131); and a passive device located at least partially in the first encapsulation layer, wherein the first encapsulation layer and the passive device are located between the first metallization portion and the second metallization portion (Fig. 15, local interconnect component 1534, glass core 1551; ¶127-131).
Regarding claim 17, Duan further teaches a laminated substrate coupled to the package (Fig. 29, circuit board 2902; ¶226 -236).
Regarding claim 18, Duan further teaches a board coupled to the package (Fig. 29, circuit board 2902; ¶226 -236).
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Regarding claim 19, Duan further teaches the passive device comprising a trench capacitor device (Figs. 4B & 15, local interconnect component 1534, local interconnect component 435, trench capacitor 456; ¶80-81, 127-131).
Regarding claim 20, Duan further teaches the device being one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (Fig. 30, electrical device 3000; ¶251).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duan in view of We et al. (Pub. No. US 20220375838 A1), hereinafter referred to as We.
Regarding claim 4, Duan teaches the package of claim 1, wherein the passive device is coupled to the first metallization portion (Fig. 15, local interconnect component 1534, stacked dielectric layers 1522; ¶127-131). However, Duan does not explicitly teach the passive device being coupled to the first metallization portion through a plurality of solder interconnects.
We teaches the passive device being coupled to the first metallization portion through a plurality of solder interconnects (Figs. 2 & 3, bridge 108, solder interconnects 284, solder interconnects 286, metallization portion 106, metallization portion 306; ¶27, 33-41).
Duan and We are analogous art as they are in the same field of endeavor of semiconductor packaging and devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Duan to incorporate the solder interconnects of We such that the passive device is coupled to the first metallization portion through a plurality of solder interconnects. For the purpose of gaining benefits of using solder interconnects such being able to use established manufacturing techniques and infrastructure, thermal and power management, strong bonding between components, high electrical conductivity, and/or its lower manufacturing cost.
Regarding claim 5, Duan further teaches the passive device being coupled to the second metallization portion (Fig. 15, stacked dielectric layers 1524, local interconnect component 1534; ¶127-131). However, Duan does not explicitly teach the passive device is coupled to the second metallization portion through a plurality of solder interconnects.
We teaches the passive device being coupled to the second metallization portion through a plurality of solder interconnects (Figs. 2 & 3, bridge 108, solder interconnects 284, solder interconnects 286, metallization portion 106, metallization portion 306; ¶27, 33-41).
Duan and We are analogous art as they are in the same field of endeavor of semiconductor packaging and devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Duan to incorporate the solder interconnects of We such that the passive device is coupled to the second metallization portion through a plurality of solder interconnects. For the purpose of gaining benefits of using solder interconnects such being able to use established manufacturing techniques and infrastructure, thermal and power management, strong bonding between components, high electrical conductivity, and/or its lower manufacturing cost.
Regarding claim 11, Duan teaches the package of claim 8, wherein the bridge is coupled to the second metallization portion (Fig. 15, stacked dielectric layers 1524, local interconnect component 1534; ¶127-131). However, Duan does not explicitly teach the bridge being coupled to the second metallization portion through a plurality of solder interconnects.
We teaches the bridge being coupled to the second metallization portion through a plurality of solder interconnects (Figs. 2 & 3, bridge 108, solder interconnects 284, solder interconnects 286, metallization portion 106, metallization portion 306; ¶27, 33-41).
Duan and We are analogous art as they are in the same field of endeavor of semiconductor packaging and devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Duan to incorporate the solder interconnects of We such that the bridge is coupled to the second metallization portion through a plurality of solder interconnects. For the purpose of gaining benefits of using solder interconnects such being able to use established manufacturing techniques and infrastructure, thermal and power management, strong bonding between components, high electrical conductivity, and/or its lower manufacturing cost.
Regarding claim 12, Duan does not explicitly teach an electrical path between the first metallization portion and the second metallization portion including the passive device.
We teaches an electrical path between the first metallization portion and the second metallization portion including the passive device (Fig. 3, metallization portion 106, pillar interconnects 112, bridge 108, pillar interconnects 114, pillar interconnects 312, metallization portion 306; ¶27, 33-41).
Duan and We are analogous art as they are in the same field of endeavor of semiconductor packaging and devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Duan to incorporate the teachings of We to have an electrical path between the first metallization portion and the second metallization portion include the passive device. For the purpose of having a shorter electrical path between integrated devices to help improve performance of the integrated devices and the package, as recognized by We.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
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