DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, readable in claims 1-5, 7-12 and 14-18 in the reply filed on 6/27/2026 is acknowledged. In the traversal, the applicant argues that:
- Two distinct inventions (Species I and II) as claimed is not a serious burden to consider only twenty claims and with only two (2) claims being independent in a single patent application.
- A review of the subject matter set forth in the claims shows that they are substantially related.
This is not found persuasive because the search needed to find relevant prior art to one of the Species, doesn’t necessarily yield results for the other Species. Species I is directed to an invention where calculations, such as the calculation of average voltage, is performed using computer implemented algorithms and logic. On the other hand, Species II appears to perform said functions using an integrator (see for example claim 6). Although substantially related, prior art applicable to Species I would not necessarily be applicable to Species II. Examination of two separate and independent species, search in consideration of patentability and consideration of the scope as it relates to patent eligibility pose a serious burden on the examiner (for example, the claims do not appear compliant with 35 USC 112(b) and 35 USC 101 as noted in the body of the Office Action presented below). The examiner respectfully notes that the claim set includes three (3) independent claims, not two.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the voltage regulator comprising circuitry configured to sense a load current on the load line and circuitry configured to calculate a new output voltage to be output on the load line, as recited in claim 10 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 8 is objected to because of the following informalities:
In line 9, the recitation "arithmetic logic configured use at least" should be replaced with: “arithmetic logic configured to use at least”. Appropriate correction is required.
Claims 9-12 and 14 are also objected as they inherit the informality noted above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 7-12 and 14-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites: “sensing an average of an output voltage”. The recitation is unclear insofar as an average, as understood by a person having ordinary skill in the art, is computed or estimated, not sensed. That is, while a sensor may detect voltage, in order to arrive at an “average”, a plurality of detected values must be added and then divided by said number of values. A sensor itself doesn’t provide an “average” without some processing of the detected values.
For the purpose of examination, the examiner interprets the claim as reciting:
- sensing and averaging an output voltage
Correction is required.
Claims 2-5 and 7 are also rejected as they inherit the deficiencies noted above.
Similarly, with regards to claim 8, the recitation: “voltage sensing and averaging circuitry configured to sense an average of the output voltage” appears misleading because, as explained in regards to claim 1 above, an “average” is not “sensed” but rather calculated. For the purpose of examination, the examiner interprets claim 8 as reciting”
- voltage sensing and average circuitry configured to sense an output voltage delivered to the subsystem over a predetermined time period and to calculate an average of the output voltage over the predetermined time period;
Claims 9-12 and 14 are also rejected as they inherit the deficiencies noted above.
Regarding claim 10, the claim recites: “the voltage regulator comprises circuitry configured to sense a load current on the load line and circuitry configured to calculate a new output voltage to the output on the load line based at least in part on the sensed load current.” It’s not clear if the recited sensed load current is the same as the calculated load current recited in claim 8, or if it refers to a value that is independently sensed by the voltage regulator. It appears the voltage regulator receives an indication of load current calculated by the subsystem of the SoC (see Specification, paragraph 0031, last 5 lines). Thus, the circuitry doesn’t appear to sense the load current, but rather receive a value related to the load current as calculated by the subsystem. The examiner kindly requests clarification about the recitation “circuitry configured to sense a load current on the load line”, and specifically the intended meaning of the word “sense”.
Regarding claim 15, the recitation “the subsystem of the SoC” in line 3 lacks antecedent basis. Moreover, the preamble doesn’t appear to clearly define whether the recited “processing logic for executing computer instructions” (as recited in lines 4-5) refers to logic processing that perform the claimed computer program, or a separate set of processing logic. Claim 15 recites:
“15. A computer program for performing rail power telemetry in a system-on-a-chip (SoC), the computer program being embodied on a non-transitory computer readable medium, wherein a voltage regulator delivers an output voltage to the subsystem of the SoC via a load line, and wherein each of the subsystems comprises processing logic for executing computer instructions, the computer instructions comprising:
a first set of computer instructions for obtaining an average of the output voltage delivered to the subsystem over a predetermined time period; and
a second set of computer instructions for calculating a load current on the load line based at least on the average of the output voltage calculated by the first set of computer instructions.”
Because the recitation “the subsystem of the SoC is not clearly introduced as being a part of the system-on-chip, the processing logic in the subsystems may be interpreted as logic in a separate circuit, and not necessarily on the system-on-a-chip. Also, the claim introduces a singular subsystem of the SoC, but then refers to “each of the subsystems”.
For the purpose of examination, the examiner interprets the claim as reciting:
“15. A computer program for performing rail power telemetry in a system-on-a-chip (SoC), the computer program being embodied on a non-transitory computer readable medium, wherein a voltage regulator delivers an output voltage to a plurality of subsystems of the SoC via a load line, and wherein each of the plurality of subsystems comprises processing logic for executing computer instructions, the computer instructions comprising:
a first set of computer instructions for obtaining an average of the output voltage delivered to the subsystem over a predetermined time period; and
a second set of computer instructions for calculating a load current on the load line based at least on the average of the output voltage calculated by the first set of computer instructions.”
Correction is required. Claims 16-18 are also rejected as they inherit the deficiencies noted above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5 and 7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, the claim includes the recitation:
-- sensing and averaging (see claim rejection under 35 USC 112b above) an output voltage delivered to the subsystem over a predetermined time period over a load line by a voltage regulator; and
using at least the average of the output voltage to calculate a load current on the load line.--
The claim is ineligible under 35 USC 101. The following analysis is consistent with the procedures outlined on the 2019 Revised Patent Subject Matter Eligibility Guidance.
Step 1: Is the claim to a process, machine or composition of matter? Yes. The claim is to a method.
Step 2A, PRONG ONE: Does the claim recite an abstract idea, law of nature, or Natural Phenomenon? – Yes. The claim is directed to a process for calculating an average of sensed signals and using said value to calculate a load current on a load line. The limitations, as drafted are directed to a computation/process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “in a subsystem of the SoC”, nothing in the claim element precludes the step from practically being performed in the mind, or using a pen and paper. The mere nominal recitation of a “subsystem of the SoC” does not take the claim limitation out of the mental processes grouping. Thus, the claim recites a mental process.
Step 2A, PRONG TWO: Does the claim recite additional elements that integrate the judicial exception into a practical application? – No. Although the claim recites the steps are performed “in a subsystem of the SoC”, the subsystem is recited at a high level of generality, i.e., as a generic processor performing a generic computer function of processing data. Moreover, the claim doesn’t explicitly describe elements within the “subsystem of the SoC” which perform the calculations. The recitation appears thus, to be no more than mere instructions to apply the exception using a generic computer component. Accordingly, the additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
- Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception? – No. As discussed with respect to Step 2A Prong Two, the additional element in the claim amounts to no more than mere instructions to apply the exception using a generic computer component or within a generic computing subsystem. The same analysis applies here in 2B, i.e., mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
As to claims 2, 5 and 7, the claims describe additional computational steps directed to processing of signals (abstract idea) that can be performed in the human mind and/or using a pen and a piece of paper. The claims do not recite steps or actions that integrate the judicial exception into a practical application. Moreover, the claims do not appear to recite additional elements that among to significantly more than the judicial exception. Thus, the claims are rejected for the same reasons outlined in regards to claim 1.
As to claims 3-4, claim 3 recites circuitry comprised within a voltage regulator for sensing a load current on the load line and for calculating a new output voltage. Claim 4 recites the steps of sensing a load current on the load line and using the sensed load current and a know slope to determine new output voltage. Similar to that described above, the recitations are directed to a process that can be readily be performed in the human mind, or using tools such as a piece of paper and pen. The recited “circuitry” is recited at a high level of generality and its function (gathering data, manipulate the data, output a result), is considered extra solution activity. Furthermore, the claims do not recite additional elements that amount to significantly more than the judicial exception as the elements (circuitry) are recited at a high level of generality.
Claims 8-12 and 14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 8, the claim includes the recitation:
-- at least one subsystem disposed on the SoC and electrically coupled to a load line over which an output voltage is delivered to the subsystem by a voltage regulator, the subsystem comprising:
voltage sensing and average circuitry configured to sense an output voltage delivered to the subsystem over a predetermined time period and to calculate an average of the output voltage over the predetermined time period (see rejection under 35 USC 112(b) above); and
arithmetic logic configured use at least the average of the output voltage to calculate a load current on the load line. --
The claim is ineligible under 35 USC 101. The following analysis is consistent with the procedures outlined on the 2019 Revised Patent Subject Matter Eligibility Guidance.
Step 1: Is the claim to a process, machine or composition of matter? Yes. The claim is to a system.
Step 2A, PRONG ONE: Does the claim recite an abstract idea, law of nature, or Natural Phenomenon? – Yes. The claim is directed to a process for calculating an average of sensed signals and using said value, calculating a load current on the load line. The limitations, as drafted, are directed to a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “at least one subsystem” comprising “voltage sensing and averaging circuitry”, as well as “arithmetic logic”, nothing in the claim element precludes the step from practically being performed in the mind, or using a pen and paper. The mere nominal recitation of a “circuitry and/or arithmetic logic” does not take the claim limitation out of the mental processes grouping. Thus, the claim recites a mental process.
Step 2A, PRONG TWO: Does the claim recite additional elements that integrate the judicial exception into a practical application? – No. Although the claim describes the sensing, averaging and calculations are performed by “circuitry” and “arithmetic logic” of a system-on-a-chip (SoC), the circuitry and arithmetic logic are recited at a high level of generality, i.e., as a generic circuit/processor performing a generic gathering of signals, and generic components performing the calculation of load current. Thus, the recitation appears to be no more than the application of the exception using a generic computer component. Accordingly, the additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
It’s noted that the claim doesn’t positively recite the “voltage regulator” as being part of the system, but rather as a component that the recited system is intended to be used/paired with. As recited, it doesn’t appear to impose any meaningful limits on the recited calculation of voltage average or load current value.
- Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception? – No. As discussed with respect to Step 2A Prong Two, the additional element in the claim amounts to no more than mere instructions to apply the exception using a generic computer component. The same analysis applies here in 2B, i.e., mere instructions to apply an exception using a generic computer component (voltage sensing and averaging circuitry, arithmetic logic) cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
As to claims 9-12 and 14, the claims describe additional computational steps directed to processing of signals (abstract idea) that can be performed in the human mind and/or using a pen and a piece of paper. The claims do not recite steps or actions that integrate the judicial exception into a practical application. Moreover, the claims do not appear to recite additional elements that among to significantly more than the judicial exception. Also, the recited “voltage sampling circuit” and “logic” as recited in claim 12, is described at a high level of generality. Thus, the claims are rejected for the same reasons outlined in regards to claim 8.
Claims 15-18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 15, recites:
-- 15. A computer program for performing rail power telemetry in a system-on-a-chip (SoC), the computer program being embodied on a non-transitory computer readable medium, wherein a voltage regulator delivers an output voltage to a plurality of subsystems of the SoC via a load line, and wherein each of the plurality of subsystems (see rejection under 35 USC 112(b) above) comprises processing logic for executing computer instructions, the computer instructions comprising:
a first set of computer instructions for obtaining an average of the output voltage delivered to the subsystem over a predetermined time period; and
a second set of computer instructions for calculating a load current on the load line based at least on the average of the output voltage calculated by the first set of computer instructions.”
The claim is ineligible under 35 USC 101. The following analysis is consistent with the procedures outlined on the 2019 Revised Patent Subject Matter Eligibility Guidance.
Step 1: Is the claim to a process, machine or composition of matter? Yes. The claim is directed to a computer embodied on a non-transitory computer readable medium (apparatus).
Step 2A, PRONG ONE: Does the claim recite an abstract idea, law of nature, or Natural Phenomenon? – Yes. The claim is directed to a process for calculating an average of sensed signals and using said value, calculating a load current on the load line. The calculations are performed by executing computer instructions on a computational system. The limitation, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “by processing logic”, nothing in the claim element precludes the step from practically being performed in the mind, or using a pen and paper. The mere nominal recitation of a generic processing logic does not take the claim limitation out of the mental processes grouping. Thus, the claim recites a mental process.
Step 2A, PRONG TWO: Does the claim recite additional elements that integrate the judicial exception into a practical application? – No. Although the claim recites processing logic for executing the computer instructions, the processing logic is recited at a high level of generality, i.e., as a generic processor performing a generic computer function of processing data. This generic processing logic limitation is no more than mere instructions to apply the exception using a generic computer component. Accordingly, the additional element does not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
- Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception? – No. As discussed with respect to Step 2A Prong Two, the additional element in the claim amounts to no more than mere instructions to apply the exception using a generic computer component. The same analysis applies here in 2B, i.e., mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
As to claims 16-18, the claims describe additional computational steps directed to processing of signals (abstract idea) that can be performed in the human mind and/or using a pen and a piece of paper. The claims do not recite steps or actions that integrate the judicial exception into a practical application. Moreover, the claims do not appear to recite additional elements that among to significantly more than the judicial exception. Thus, the claims are rejected for the same reasons outlined in regards to claim 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5, 8, 12, 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the US Patent US 6,489,834 by Naffziger et al., (Naffziger hereafter) in view of the US Patent Application Publication PGPub 2012/0092896 A1 by Hachiya et al., (Hachiya hereafter).
Regarding claim 1, Naffziger teaches a method for performing rail power telemetry in a system-on-a-chip (SoC), the method comprising: in a subsystem of the SoC (system within chip 106, see Figure 1):
sensing an average of an output voltage (VAVERAGE) delivered to the subsystem over a predetermined time period over a load line by a voltage regulator (102); and
using at least the average of the output voltage to calculate a current consumption of the chip (power consumption, see col. 8, lines 20-29)
Naffziger substantially teaches all of the elements disclosed above, except for explicitly mentioning calculating input current using the average voltage.
Hachiya teaches in a method for calculating input current on a circuit, by using a value of average voltage (see paragraph 0015). It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of using the value of average voltage as taught by Hachiya, in the device/system/method of Naffziger, in order to determine the value of current inputted to the chip periodically, thereby ascertaining whether the chip receives excessive current at any given time and take corrective actions as needed, thus preventing damage to the chip.
As to claim 3, the claim appears to describe functional and structural characteristics of the voltage regulator. The claim doesn’t appear to describe a step that links the method recited in claim 1 to the functional/characteristics of the voltage regulator. For example, the claim doesn’t include a step where the voltage regulator senses a load current on the load line, or a step of calculating a new output voltage, or a step of delivering the new output voltage.
Moreover, the examiner notes that the recitation “for sensing a load current” appears to refer to a value of load current that is sensed by the voltage regulator and which is separate from the value of load current calculated in the subsystem of the SoC. Thus, the claim appears to simply state capabilities of a voltage regulator that have no apparent effect on the method steps recited in claim 1. Thus, because the prior art in combination teaches the steps as recited, the prior art in combination meets the claim.
Regarding claim 5, Naffziger and Hachiya are silent about the process of calculating an average including taking N samples the voltage over time, summing and diving the values by N. However, Official Notice is taken to the fact a person having ordinary skill in the art would have found it obvious, before the effective filing date of the claimed invention, to use the well-known method for averaging a sensed signal over time, and applying it to the method of Naffziger in view of Hachiya, in order to calculate the average value of voltage that, as Hachiya teaches, is used in the calculation of load current.
Regarding claim 8, Naffziger teaches in Figure 1, a system for performing rail power telemetry in a system-on-a-chip (SoC), the system comprising:
at least one subsystem disposed on the SoC (subsystem within chip 106) and electrically coupled to a load line (line connecting 102 to 106) over which an output voltage is delivered to the subsystem by a voltage regulator (102), the subsystem comprising:
- voltage sensing and average circuitry (113+114) configured to sense an output voltage delivered to the subsystem over a predetermined time period and to calculate an average of the output voltage over the predetermined time period (VAVERAGE); and
arithmetic logic (within 112 and 108) configured to use at least the average of the output voltage to calculate a current consumption (col. 8, lines 19-29).
Naffziger substantially teaches all of the elements disclosed above, except for explicitly mentioning calculating input current using average voltage.
Hachiya teaches in a method for calculating input current on a circuit, by using a value of average voltage (see paragraph 0015). It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of using the value of average voltage as taught by Hachiya, in the device/system/method of Naffziger, in order to determine the value of current inputted to the chip periodically, thereby ascertaining whether the chip receives excessive current at any given time and take corrective actions as needed, thus preventing damage to the chip.
Regarding claim 12, Naffziger and Hachiya are silent about the process of calculating an average including taking N samples the voltage over time, summing and diving the values by N. However, Official Notice is taken to the fact a person having ordinary skill in the art would have found it obvious, before the effective filing date of the claimed invention, to use the well-known method for averaging a sensed signal over time, and applying it to the method of Naffziger in view of Hachiya, in order to calculate the average value of voltage that, as Hachiya teaches, is used in the calculation of load current.
Regarding claim 15, as explained in the rejection of claim 1 above, Naffziger in view of Hachiya teaches a process by which a load current is calculated. Furthermore, Hachiya teaches the use of a control part (19) that includes a microcomputer (see paragraph 0031). The control part calculating the average voltage and load current (see paragraph 0015). Although Hachiya doesn’t explicitly mention the microprocessor includes a computer program for performing the calculation, the program is inherently present in the microprocessor, since microprocessors are incapable of performing tasks without a set of instructions stored therein.
Regarding claim 17, Naffziger and Hachiya are silent about the process of calculating an average including taking N samples the voltage over time, summing and diving the values by N. However, Official Notice is taken to the fact a person having ordinary skill in the art would have found it obvious, before the effective filing date of the claimed invention, to use the well-known method for averaging a sensed signal over time, and applying it to the method of Naffziger in view of Hachiya, in order to calculate the average value of voltage that, as Hachiya teaches, is used in the calculation of load current.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
- The US Patent US 9,829,948 by DiBene, II et al. directed to systems on chip including means for measuring current and providing feedback to a power supply.
- The US Patent US 10,948,537 by Forrest et al., directed to integrated circuits including circuitry for determining load current based on detected voltage.
- The US Patent Application Publication PGPub 2022/0082595 by Clayton et al., directed to on-chip circuits, including current sensing circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Richard Isla whose telephone number is (571)272-5056. The examiner can normally be reached Monday-Friday 9a - 5:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICHARD ISLA/ Primary Patent Examiner, Art Unit 2858 August 11, 2026
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