DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 5/6/2024 and 4/17/2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I and Species 1 in the reply filed on 7/20/2026 is acknowledged.
Claims 3 and 11-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species/invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/20/2026.
Claim Objections
Claim 5 is objected to because of the following informalities:
Re Claim 5, lines 2-3 recite “the dielectric layer” where it is not completely clear whether it is in reference to “an inter-gate dielectric layer” in line 13 of Claim 1 or “a dielectric layer” in line 2 of Claim 5 (an additional adjective for “a dielectric layer” would make it clear). For the purposes of examination, “the dielectric layer” in lines 2-3 of Claim 5 will be assumed to be referring to “a dielectric layer” in line 2 of Claim 5.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 and 4-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re Claim 1, lines 14-15 recite “a plurality of drain regions formed in the semiconductor epitaxial layer on both sides of the control gate”, where it is unclear what “both sides” are referring to, as no sides of the control gate were otherwise recited in Claim 1. For the purposes of examination, “both sides” will be interpreted to mean “opposing sides”.
In Re Claims 2 and 4-10, they are rejected due to their dependence from rejected Claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakagawa (US 2001/0039091 A1).
Re Claim 1, Nakagawa discloses a non-volatile memory device (FIG. 4J; [0040]-[0050]), comprising:
a substrate (21, 24; [0039]);
a source line (24; [0039]) formed in the substrate (21, 24; [0039]);
a semiconductor epitaxial layer (25; [0039]) formed on the substrate (21, 24; [0039]);
a device isolation structure (26, 39; [0043], [0050]) formed in the semiconductor epitaxial layer (25; [0043], in part) and extending in a first direction (left to right across page in FIG. 4J; [0050], particularly portion 39);
a trench (at least 30, 32; [0039]) formed in the semiconductor epitaxial layer (25; [0039]) and crossing the device isolation structure (26, 39; [0039]) in a second direction (into page of FIG. 4J; [0039]), wherein a bottom portion of the trench (at least 30, 32) exposes the source line (24; [0039]);
a floating gate (34; [0039]) disposed in the trench (at least 30, 32; [0039]);
a tunnel oxide layer (33; [0039]) disposed between the floating gate (34) and the source line (24; [0039]);
a control gate (38; [0039]) disposed above the floating gate (34; [0039]) and extending in the second direction (into page of FIG. 4J; [0039]);
an inter-gate dielectric layer (36; [0039]) disposed between the floating gate (34) and the control gate (38; [0039]);
a plurality of drain regions (28; [0039]) formed in the semiconductor epitaxial layer (25; [0039]) on both sides of the control gate (38; [0039]); and
a bit line (40; [0039]) extending on the semiconductor epitaxial layer (25) in the first direction (left to right across page in FIG. 4J; [0050]) and electrically connected to the plurality of drain regions (28; [0039]).
Re Claim 4, Nakagawa discloses the non-volatile memory device according to Claim 1, while further disclosing wherein a top portion of the control gate (38, “top portion”, see FIG. Z1 below; [0039], top portion, as it is in top half of the control gate) is lower than a top portion of the trench (at least 30, 32, uppermost corner; [0039]).
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FIG. Z1: Annotated version of FIG. 4J of Nakagawa
Re Claim 6, Nakagawa discloses the non-volatile memory device according to Claim 1, while further disclosing wherein the trench (30, 32, and space taken up by “oxide film” below bottom surface of 39; [0050]) has a first depth at a location where the floating gate (34) is formed (“first depth”, see FIG. Z2 below; [0039]), the trench (30, 32, and space taken up by “oxide film” below bottom surface of 39) has a second depth at a location where the trench (30, 32, and space taken up by “oxide film” below bottom surface of 39) intersects the device isolation structure (26, 39, “second depth”, see FIG. Z2 below; [0050]), and the first depth is greater than the second depth ([0050]).
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FIG. Z2: Annotated version of FIG. 4J of Nakagawa
Re Claim 7, Nakagawa discloses the non-volatile memory device according to Claim 1, while further disclosing wherein the bit line (40) is in direct contact with the plurality of drain regions (28; [0039], electrical contact).
Re Claim 8, Nakagawa discloses the non-volatile memory device according to Claim 1, while further disclosing wherein the tunnel oxide layer (33) further extends between the floating gate (34) and the semiconductor epitaxial layer (25; [0039]).
Re Claim 9, Nakagawa discloses the non-volatile memory device according to Claim 1, while further disclosing wherein the inter-gate dielectric layer (36) further extends between the control gate (38) and the plurality of drain regions (28; [0039]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa, as applied to Claim 1, in view of Thomas (US 5675161 A).
Re Claim 2, Nakagawa discloses the non-volatile memory device according to Claim 1, while further disclosing wherein the source line (24) overlaps the bit line (40; [0039], at least in part).
Nakagawa does not explicitly disclose wherein the source line (24) extends in the first direction (left to right across page in FIG. 4J).
However, Thomas discloses a non-volatile memory device (FIG. 3; column 3, line 27 to column 4, line 2) comprising wherein the source line (2; column 3, lines 27-54) extends in the first direction (left to right across page in FIG. 3; column 3, line 66 to column 4, line 2).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the non-volatile memory device according to Claim 1 with the limitations taught by Thomas to utilize an alternate configuration wherein the source line (Nakagawa: 24) extends in the same first direction as the bit line (Nakagawa: 40) to have coordinated programming of bits along the first direction as taught by Thomas (column 3, line 66 to column 4, line 2).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa, as applied to Claim 1, in view of Schaijk et al (US 2006/0220093 A1, hereafter Schaijk).
Re Claim 10, Nakagawa discloses the non-volatile memory device according to Claim 1, but does not explicitly disclose wherein the inter-gate dielectric layer (36) comprises a high dielectric constant (high-k) layer or an ONO layer.
However, Schaijk discloses a non-volatile memory device (FIG. 12; [0081]-[0090]) wherein the inter-gate dielectric layer (12; [0083]) comprises a high dielectric constant (high-k) layer or an ONO layer ([0084]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the non-volatile memory device according to Claim 1 with the limitations taught by Schaijk to substitute the material for the inter-gate dielectric layer (Nakagawa: 36) with a high dielectric constant (high-k) layer or an ONO layer as functionally equivalent means of providing dielectric separation between the floating gate (Nakagawa: 34) and the control gate (Nakagawa: 38) as taught by Schaijk ([0087]).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable (assuming the outstanding objection of Claim 5 and 112(b) rejection of Claim 1 was addressed) if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 5, the prior art cannot anticipate, or render obvious, the limitations of: wherein the dielectric layer fills the trench, in combination with the additionally claimed features of Claim 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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