DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-16) in the reply filed on July 14, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 7-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (11,658,069).
Re claim 1, Chen et al. disclose a top portion of a through-silicon-via hole (44) on a semiconductor substrate (22) (Fig. 3); a dielectric liner (50) surrounding a sidewall of the top portion of the through-silicon-via hole; and a through-silicon-via encapsulation (40) surrounding the dielectric liner (Fig. 10).
Re claim 2, Chen et al. disclose further comprising: an interlayer dielectric material (ILD) (Col. 4, lines 5-15) contacting an outside surface of a sidewall of the through-silicon-via encapsulation (40); a plurality of front side interconnect wiring layers (24) electrically isolated from the through-silicon-via encapsulation (40) by the interlayer dielectric material (ILD); and a bottom portion of the through-silicon-via hole (64A) in the semiconductor substrate (22) (Fig. 13).
Re claim 3, Chen et al. disclose wherein: the through-silicon-via encapsulation (40) is composed of a metal nitride material (Col. 5, lines 30-32); and the dielectric liner (50) is composed of an oxide dielectric material (Col. 6, lines 15-23).
Re claim 4, Chen et al. disclose wherein the through-silicon-via encapsulation (40) reduces moisture ingress into one or more of the plurality of front side interconnect wiring layers (24) (same materials are treated in the same manner).
Re claim 5, Chen et al. disclose wherein: a bottom surface of each of the through-silicon-via encapsulation (40) and the dielectric liner (50) each reside on a top surface of the semiconductor substrate (22) (both coexist on a top surface of the semiconductor substrate); and a top surface of each of the through-silicon-via encapsulation (40) and the dielectric liner (50) are level with a top surface of the plurality of front side interconnect wiring layers (24) (Fig. 13).
Re claim 7, Chen et al. disclose wherein the through-silicon-via encapsulation (40) and the dielectric liner (50) are a cylindrical capacitor around the top portion of the through-silicon-via hole (parasitic capacitor).
Re claim 8, Chen et al. disclose wherein the dielectric liner (50) is composed of a high k dielectric material (aluminum oxide ~ Col. 6, line 23).
Re claim 9, Chen et al. disclose wherein the through-silicon-via encapsulation is grounded (the TSV encapsulation is electrically isolated from the front side interconnect wiring 24 by a portion of the ILD).
Re claim 10, Chen et al. disclose a top portion of a through-silicon-via (TSV) (64A) above a top surface of a semiconductor substrate (102) (Fig. 16); a dielectric liner (50) surrounding a sidewall of the top portion of the TSV, wherein the dielectric liner (50) resides on the top surface of the semiconductor substrate (102); and a TSV encapsulation (40) surrounding a sidewall of the dielectric liner (50), wherein the TSV encapsulation (40) resides on the top surface of the semiconductor substrate (102).
Re claim 11, Chen et al. disclose further comprising: a bottom portion of the TSV (64A) in the semiconductor substrate (22); and a first interlayer dielectric material (ILD) surrounding an outside surface of a sidewall of the TSV encapsulation (40) and a sidewall of the semiconductor substrate (22) in the bottom portion of the TSV.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. as applied to claims 1-5 and 7-11 above, and further in view of Chung et al. (2022/0102369).
Re claim 6, Chen et al. does not clearly disclose wherein the through-silicon-via encapsulation and the dielectric liner each have a circular horizontal cross-section.
However, it would have been an obvious matter of design choice bounded by well known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re claim 12, Chen et al. does not disclose further comprising: a moisture oxidation collar on the top surface of the semiconductor substrate, wherein: the moisture oxidation collar resides outside of the first interlayer dielectric material around the TSV encapsulation; and a second interlayer dielectric material separates the moisture oxidation collar from a plurality of front side interconnect wiring layers surrounding the second interlayer dielectric material.
Chung et al. disclose a moisture oxidation collar (GR- ground ring- Fig. 3A & [0038]) on the top surface of the semiconductor substrate (11), wherein: the moisture oxidation collar (GR) resides outside of the first interlayer dielectric material (190) around the TSV encapsulation; and a second interlayer dielectric material separates the moisture oxidation collar from a plurality of front side interconnect wiring layers surrounding the second interlayer dielectric material (Fig. 3A).
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Chen et al. and Chung et al. to enable the ground ring as taught by Chung et al. to be added to Chen et al.'s device to act as a moisture oxidation barrier structure preventing moisture to get into the structure.
Re claim 13, Chen et al. does not clearly disclose wherein the moisture oxidation collar has a rectangular horizontal cross-section and the TSV encapsulation has a circular horizontal cross-section.
However, it would have been an obvious matter of design choice bounded by well known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re claim 14, Chen et al. disclose wherein the through-silicon-via encapsulation (40) and the dielectric liner (50) are a cylindrical capacitor around the top portion of the through-silicon-via hole (parasitic capacitor).
Re claim 15, Chen et al. disclose wherein the through-silicon-via encapsulation is grounded (the TSV encapsulation is electrically isolated from the front side interconnect wiring 24 by a portion of the ILD).
Re claim 16, Chen et al. disclose wherein the dielectric liner contacts a top surface of the TSV encapsulation, the interlayer dielectric material (Fig. 10). The combination discloses wherein the liner would contact a moisture oxidation collar (GR of Chung et al.) as explained in claim 12 above.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2024/0339399 A1, US 2022/0148995 A1 disclose a similar configuration for a semiconductor structure with a through silicon via (TSV).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE MANDALA whose telephone number is (571)272-1858. The examiner can normally be reached 8:00-5:00 PM.
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/MICHELLE MANDALA/Primary Examiner, Art Unit 2893 August 19, 2026
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