Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/06/24 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I, claims #1-8 in the reply filed on 07/27/26 is acknowledged.
Claims #1-8 will be further examined.
Newly submitted claims #21-32 (claim #21-26 as Group II and claims #27-31 as Group III) are directed to inventions that are independent or distinct from the invention originally claimed (claims #1-8-Group I) for the following reasons:
Inventions Group I and Group II are directed to related structures. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed by the structure of Group II can be practiced for it's intended purpose without requiring wherein a first number of metallization layers of the multilayer interconnection structure directly above the peripheral circuit is greater than a second number of metallization layers of the multilayer interconnection structure directly above the semiconductor detector, which is required by the claimed structure of Group I. Also, the invention as claimed in Group I can be practiced for it's intended purpose without requiring structure wherein a word line coupled to gates of the first transistors of the first and second detector units, as required by the invention of the Group II claim language. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Inventions Group I and Group III are directed to related structures. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed by the structure of Group III can be practiced for it's intended purpose without requiring a requiring wherein a first number of metallization layers of the multilayer interconnection structure directly above the peripheral circuit is greater than a second number of metallization layers of the multilayer interconnection structure directly above the semiconductor detector, which is required by the claimed structure of Group I. Also, the invention as claimed in Group I can be practiced for it's intended purpose without requiring a multilayer interconnect structure over the substrate and having more metallization layers directly above the peripheral circuit than directly above the semiconductor detector, as required by the invention of the Group III claim language. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Since applicant has received an action on the merits of the restrictive nature of the original claims and has chosen without traverse to have prosecuted that specifically claimed invention, the originally presented invention, has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims #21-32 are withdrawn from consideration as being directed to a non-elected invention, a shown above in the present action. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claims #1-8 will be further examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) #1, 5-8 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Ellis-Monaghan et al., (U.S. Pub. No, 2007/0235780), hereinafter referred to as "Monaghan".
Monaghan shows, with respect to claim #1, a semiconductor structure, comprising: a substrate (fig. #4B, item 200) (paragraph 0032) having a sensing region (fig. #4B, item T2) and a peripheral region (fig. #6A, item 245) (paragraph 0036); a semiconductor detector on the sensing region of the substrate (paragraph 0024), the semiconductor detector comprising: a first detector unit (fig. #1, item 100) (paragraph 0030), a second detector unit (fig. #3, item 115) (paragraph 0034), and a third detector unit (fig. #3, item 122) (paragraph 0026), each of the first, second, third detector units comprising a first transistor and a second transistor (Transistors T1, T2) connected in series (paragraph 0007, 0026), wherein a gate of the second transistor is a floating gate (paragraph 0007-0008, 0032); a peripheral circuit (fig. #6A, item P-WELL EX.) on the peripheral region (fig. #6A, item 245) of the substrate (fig. #6C, item 200) and coupled to the semiconductor detector (fig. #6A, item T1&T2) (paragraph 0031-0032); and a multilayer interconnection structure (fig. #4B, item T1&T2) over the substrate (paragraph 0030), wherein a first number of metallization layers of the multilayer interconnection structure directly above the peripheral circuit is greater than a second number of metallization layers of the multilayer interconnection structure directly above the semiconductor detector (paragraph 0030-0032).
Monaghan shows, with respect to claim #5, a semiconductor structure, further comprising: a first word line coupled to gates of the first transistors of the first and second detector units; a source line coupled to sources of the first transistors of the first, second, third detector units; and a first bit line coupled to drains of the second transistors of the first and third detector units (paragraph 0019-0020, 0024-0025).
Monaghan shows, with respect to claim #6, a semiconductor structure, wherein the semiconductor detector further comprises: a second bit line coupled to the second detector unit (paragraph 0019-0021).
Monaghan shows, with respect to claim #7, a semiconductor structure, wherein the semiconductor detector further comprises: a second word line coupled to the gate of the first transistor of the third detector unit (paragraph 0019-0021).
Monaghan shows, with respect to claim #8, a semiconductor structure, wherein the substrate is of a test wafer (fig. #4B, item 200) (paragraph 0032).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim #2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis-Monaghan et al., (U.S. Pub. No, 2007/0235780), hereinafter referred to as "Monaghan", and in view of SATO et al., (U.S. Pub. No. 2014/0159122), hereinafter referred to as "Sato".
Monaghan substantially shows the claimed invention as shown in the rejection above.
Monaghan fails to show, with respect to claim #2, a structure wherein a topmost surface of the multilayer interconnection structure directly above the sensing region of the substrate is lower than a topmost surface of the multilayer interconnection structure directly above the peripheral region of the substrate.
Sato teaches, with respect to claim #2, a structure wherein a topmost surface of the multilayer interconnection structure (Fig. # Ex1, item BC1) directly above the sensing region (Fig. # Ex1, item SR1) of the substrate is lower than a topmost surface of the multilayer interconnection structure (Fig. # Ex1, item TC1) directly above the peripheral region (Fig. # Ex1, item PR1) of the substrate (paragraph 0030, 0040).
[AltContent: textbox (Bottom Connect; BC1)]
[AltContent: ][AltContent: ][AltContent: ][AltContent: textbox (#17: Peripheral Region; PR1)][AltContent: textbox (#16: Sensing Region; SR1)][AltContent: textbox (Ex1)][AltContent: arrow][AltContent: textbox (Top Connect; TC1)][AltContent: rect]
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It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #2, to modified the invention of Monaghan as modified by the invention of Sato, which teaches, a structure wherein a topmost surface of the multilayer interconnection structure directly above the sensing region of the substrate is lower than a topmost surface of the multilayer interconnection structure directly above the peripheral region of the substrate, to incorporate a structural condition that would provide a noninvasive area for the sensing layer, as taught by Sato.
//
Claim #3, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ellis-Monaghan et al., (U.S. Pub. No, 2007/0235780), hereinafter referred to as "Monaghan", and in view of Rothberg et al., (U.S. Pat. No. 10,816,506), hereinafter referred to as "Rothberg".
Monaghan substantially shows the claimed invention shown in the rejection of claim #1 above.
Monaghan fails to show, with respect to claim #3, a structure wherein the multilayer interconnection structure further comprises a metal pad above and coupled to the gate of the second transistor of the first detector unit.
Rothberg teaches, with respect to claim #3, a structure wherein the multilayer interconnection structure further comprises a metal pad (fig. #11A, item 304) above and coupled to the gate (fig. #11A, item 164) of the second transistor (column #53, line 53-67) of the first detector unit (column # 28, line 1-23; column #30, line 59-67; column #31, line 1-5).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #3, to modified the invention of Monaghan as modified by the invention of Rothberg, which teaches, wherein the multilayer interconnection structure further comprises a metal pad above and coupled to the gate of the second transistor of the first detector unit, to incorporate a structural condition that would adhere to the sensitivity of the gate (ISFET’s) requirements, as taught by Rothberg.
Monaghan fails to show with respect to claim #4, a structure wherein the metal pad further covers the first transistor of the first detector unit.
Rothberg teaches, with respect to claim #4, a structure wherein the metal pad further covers the first transistor of the first detector unit (column # 28, line 1-23; column #30, line 59-67; column #31, line 1-5).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #4, to modified the invention of Monaghan as modified by the invention of Rothberg, which teaches, wherein the metal pad further covers the first transistor of the first detector unit, to incorporate a structural condition that would adhere to the sensitivity of the gate (ISFET’s) requirements, as taught by Rothberg.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
09/01/2026
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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