DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2017/0053844).
Re Claim 1, Tsai et al. disclose a side-exposed embedded trace substrate comprising: a dielectric layer (126 128 130 Paragraph [0021])and a first wiring layer (124 134a) embedded in the dielectric layer (126 138 130); wherein an outer surface of the first wiring layer (124 134a) is not higher than a surface of the dielectric layer (126 128 130), and the first wiring layer comprises a pad (134a, Paragraph [0025]) having a groove (not labeled, i.e., a tapered opening that formed in 134a) to increase a side-exposed area of the pad (see Fig. 1C and related text in Paragraphs [021] – [0025]).
Re Claim 2, as applied to claim 1 above, Tsai et al. disclose all the claimed limitations including wherein the groove is located at an edge or a middle of the pad (see fig. 1C).
Re Claim 3, as applied to claim 1 above, Tsai et al. disclose all the claimed limitations including wherein a depth of the groove is less than a thickness of the first wiring layer, and the pad is configured to be used to mount a device.
Re Claim 5, as applied to claim 1 above, Tsai et al. disclose all the claimed limitations including wherein the first wiring layer comprises a first sub-layer and a second sub-layer below the first sub-layer, an upper surface of the first sub-layer being flush with a surface of the dielectric layer; the groove is surrounded by the first sub-layer and exposes a dielectric layer surrounded by the second sub-layer (see Fig. 1C).
Allowable Subject Matter
Claim 4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6-13 are allowed over prior art of record.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “(b) applying a first resist layer on the substrate and forming a first opening by exposure and development, wherein the first opening exposes at least a partial region of a pad of the first wiring layer; (c) etching the first wiring layer exposed by the first opening to form a groove in a partial region of the pad,” as recited in claim 6.
Claims 7-13 are also allowed as being directly or indirectly dependent of the allowed independent base claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure ZHAI et al. (US 2016/0148904) disclose 3D integration of fanout wafer level packaging that includes pad embedded in a dielectric layer; SHARANGPANI et al. (2021/0296284) also disclose tapered shape bonding pads.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM.
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/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
July 31, 2026
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