Prosecution Insights
Last updated: October 01, 2026
Application No. 18/655,769

SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF

Non-Final OA §102§103
Filed
May 06, 2024
Examiner
ANYA, IGWE U
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
817 granted / 961 resolved
+25.0% vs TC avg
Minimal -4% lift
Without
With
+-3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
26 currently pending
Career history
970
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
36.6%
-3.4% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 961 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 17 – 20 are rejected under 35 U.S.C. 102(a(1) as being anticipated by Otto IV et al. (US 2025/0069896). (Claim 17) wherein the inner spacers further comprise a hydrogen bond or hydrocarbon compound. PNG media_image1.png 349 533 media_image1.png Greyscale (Claim 18) Otto IV et al. teach a semiconductor device, comprising: nanostructures (paragraph 26, fins) extending in a first direction above a substrate and spaced apart in a second direction perpendicular to the first direction; epitaxial source/drain regions (230, paragraph 36) on opposite sides of the nanostructures; an inner spacer (240) between adjacent two of the nanostructures, wherein the inner spacer comprises a hydrocarbon compound, a hydrogen bond or a combination thereof (paragraph 31); and a gate stack (fig. 2E #290) wrapping around the nanostructures. (Claim 19) Otto IV et al. teach wherein the inner spacer is seamless (paragraph 31, plasma deposition with precursor gas). (Claim 20) Otto IV et al. teach wherein the hydrocarbon compound comprises alcohol, alkane, alkene, alkyne, aromatic compound, ether compound, fluorinated hydrocarbon, or a combination thereof (paragraph 31). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 3, 5 – 11 and 14 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Otto IV et al. (US 2025/0069896) in view of Kim et al. (US 2023/0114933). (Claim 1) Otto IV et al. teach a method of forming a semiconductor device, comprising: forming a fin (paragraph 26) over a substrate (200), the fin comprising alternately stacked first semiconductor layers (220) and second semiconductor layers (210); etching sidewalls of the first semiconductor layers to form sidewall recesses (paragraph 30); forming a low-k dielectric material in the sidewall recesses by a chemical reaction using the dissolved precursor gases (paragraph 31); removing the first semiconductor layers (220, paragraph 48) to form spaces each between the second semiconductor layers (210, fig. 2E, paragraphs 41, 42); and filling the spaces with a gate structure (fig. 2E #290, paragraphs 49 – 51). Otto IV et al. lack: condensing a vapor-phase fill-in material into a liquid-phase solvent in the sidewall recesses; dissolving precursor gases into the liquid-phase solvent; However, Kim et al. teach: condensing a vapor-phase fill-in material into a liquid-phase solvent on a substrate; and dissolving precursor gases into the liquid-phase solvent for the benefit of achieving good coverage by employing atomic layer deposition (paragraph 93). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of achieving good coverage. (Claim 3) Otto IV et al. lack wherein the low-k dielectric material has a k value less than about 5.0 However, Kim et al. teach wherein the low-k dielectric material has a k value less than about 5.0 (paragraphs 93, 59) for the benefit of limiting and/or preventing RC delay, thereby improving reliability (paragraph 95). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of improving reliability. (Claim 5) Otto IV et al. teach wherein the low-k dielectric material comprises SiO2, SiCOBN, SiCON, or a combination thereof (paragraph 31). (Claim 6) Otto IV et al. teach wherein the vapor-phase fill-in material comprises vapor-phase water, vapor-phase alcohol, or a vapor-phase hydrocarbon compound (paragraph 31). (Claim 7) Otto IV et al. lack wherein the precursor gases comprise a silane (SiH4) gas and an H2O gas. However, Kim et al. teach wherein the precursor gases comprise a silane (SiH4) gas and an H2O gas (paragraph 93) for the benefit of limiting and/or preventing RC delay, thereby improving reliability (paragraph 95). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of improving reliability. (Claim 8) Otto IV et al. teach wherein the precursor gases are a silicon-containing precursor, an oxygen-containing precursor, a carbon-containing precursor, a boron-containing precursor, a nitrogen-containing precursor or a combination thereof (paragraph 31). (Claim 9) Otto IV et al. teach a method of forming a semiconductor device, comprising: forming a fin over a substrate, the fin comprising alternately stacked first semiconductor layers (220) and second semiconductor layers (210); etching sidewalls of the first semiconductor layers to form sidewall recesses (paragraph 30); filling the sidewall recesses with a first precursor and a second precursor such that the first precursor and the second precursor react to form inner spacers removing the first semiconductor layers to form spaces each between the second semiconductor layers; and filling the spaces with a gate structure. Otto IV et al. lack filling the sidewall recesses with a solvent; dissolving a first precursor into the solvent within the sidewall recesses; and dissolving a second precursor into the solvent within the sidewall recesses such that the first precursor and the second precursor react to form inner spacers. However, Kim et al. teach: dissolving a first precursor into a solvent on a substrate; and dissolving a second precursor into the solvent such that the first precursor and the second precursor react to form a spacer (fig. 1 #20, paragraph 93) for the benefit of limiting and/or preventing RC delay, thereby improving reliability (paragraph 95). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of improving reliability. (Claim 10) Otto IV et al. teach wherein the first precursor is a silicon-containing precursor (paragraph 31, silane). (Claim 11) Otto IV et al. teach wherein the second precursor is an oxygen-containing precursor, a carbon-containing precursor, a boron-containing precursor, a nitrogen-containing precursor, or a combination thereof (paragraph 31). (Claim 14) Otto IV et al. teach wherein the solvent comprises water, alcohol, or a hydrocarbon compound (paragraph 31). (Claim 15) Otto IV et al. teach wherein the hydrocarbon compound includes alkane, alkene, alkyne, aromatic compounds, ether compounds, fluorinated hydrocarbon, or a combination thereof (paragraph 31). (Claim 16) Otto IV et al. teach wherein the inner spacers comprise SiO2, SiCOBN, SiCON, or a combination thereof (paragraph 31). Claims 2, 4 and 12 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over Otto IV et al. (US 2025/0069896) in view of Kim et al. (US 2023/0114933) and Husson et al. (US 2022/0220132). (Claim 2) Otto IV/Kim et al. lack the method, further comprising, after forming the low-k dielectric material in the sidewall recesses, evaporating the liquid-phase solvent. However, Husson et al. teach the method, further comprising, after forming the low-k dielectric material in the sidewall recesses, evaporating the liquid-phase solvent for the benefit of removing residual solvent and volatile compounds (paragraph 246). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of removing residual solvent and volatile compounds. (Claim 4) Otto IV/Kim et al. lack wherein the liquid-phase solvent has a boiling point less than a boiling point of the low-k dielectric material. However, Husson et al. teach wherein the liquid-phase solvent has a boiling point (paragraph 237; 0 – 150 degrees C) less than a boiling point (paragraph 249; 200 – 1000 degrees C,) of the low-k dielectric material for the benefit of improving performance characteristics (paragraph 246). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of improving performance characteristics. (Claim 12) Otto IV/Kim et al. lack wherein the solvent has a boiling point less than about 300 °C. However, Husson et al. teach wherein the solvent has a boiling point less than about 300 °C for the benefit of controlling the amount of organosilane precursor vaporized (paragraph 237; 0 – 150 degrees C). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of controlling the amount of organosilane precursor vaporized (Claim 13) Otto IV/Kim et al. lack the method, further comprising: after dissolving the second precursor into the solvent within the sidewall recesses, increasing a temperature to be higher than a boiling point of the solvent. However, Husson et al. teach the method, further comprising: after dissolving the second precursor into the solvent (paragraph 243, 237), increasing the temperature to be higher than a boiling point of the solvent (paragraphs 237 – 249) for the benefit of improving performance characteristics (paragraph 246). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of improving performance characteristics. Conclusion Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IGWE U ANYA/Primary Examiner, Art Unit 2891 September 4, 2026
Read full office action

Prosecution Timeline

May 06, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
81%
With Interview (-3.7%)
2y 6m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 961 resolved cases by this examiner. Grant probability derived from career allowance rate.

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