Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/230,511, filed on 4/14/2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/6/2024 and 3/18/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "in contact with the dielectric layer" in 24. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation “the lower conductive pattern the first hard mask pattern.” It is unclear what is meant by this limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 9, 12-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Usami (US Publication No. 2018/0350760).
Regarding claim 1, Usami discloses a method of manufacturing an interconnection structure, comprising:
providing a first dielectric layer (PIQ2)
forming a hardmask layer (IF2) including a dielectric material having an etch selectivity with respect to the first dielectric layer (PIQ1) and covering an upper surface of the dielectric layer (paragraph 54)
forming a hardmask pattern by etching the hardmask layer (IF2) with a mask pattern (RP1) (Figures 5-7)
forming a via hole (OP1) and trenches (OP1) by etching the dielectric layer (PIQ1) with the mask pattern (RP1) and the hardmask pattern (IF2)
forming an interconnection pattern (MF1) covering the via hole (OP1) and the trenches (OP1)
wherein the interconnection pattern (MF1) includes a via part (MF1 in trench) covering the via hole (OP1), a pad part (MF2) vertically overlapping the via part, and a line part (PD2) extending from the pad part
wherein the bottom surface of the pad part (connected via IF2), the bottom surface of the line part (PD2), and a lateral surface (via BM3 and SD) of the via part are in contact with the dielectric layer (PIQ1)
Regarding claim 2, Usami discloses the trenches include a first trench (MF1) vertically overlapping the via hole (OP1) and a groove (BM3) extending from the first trench, wherein the pad part (MF2) fills the first trench (Figure 10, and the line part (BM3) fills the groove.
Regarding claim 3, Usami discloses a level of a bottom surface of the first trench (MF1) is higher than a level of a bottom surface (BM2) of the groove (groove is below the trench penetrating IF1).
Regarding claim 5, Usami discloses removing the mask pattern by performing an ashing process after forming the via hole and the trenches by etching the dielectric layer (paragraph 111).
Regarding claim 6, Usami discloses depositing a barrier/seed layer (SD) on the via hole (OP1) and the trenches, forming a metal layer (MF1) on the barrier/seed layer (SD), and performing a planarization process (PIQ2) on the barrier/seed layer (SD) and metal layer (MF1) (Figure 13).
Regarding claim 9, Usami discloses the first dielectric layer includes at least one of polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers (paragraph 106).
Regarding claim 12, Usami discloses a method of manufacturing an interconnection structure, comprising:
providing a lower dielectric layer (IL5)
forming a first hardmask layer (IF1) including a dielectric material having an etch selectivity with respect to the lower dielectric layer and conformally covering an upper surface of the lower dielectric layer (IL5) (paragraph 54)
forming a first hardmask pattern (IF1) by etching the first hardmask layer with a first mask pattern (Figure 7)
forming a lower hole (below OP1) by etching the lower dielectric layer (IL5) with the first mask pattern and the first hardmask pattern (IF1)
forming a lower conductive pattern (BM3) covering the lower hole (below OP1)
providing an internal dielectric layer (PIQ1) on the lower conductive pattern the first hard mask pattern (IF1)
forming a second hardmask layer (IF2) including a dielectric material having an etch selectivity with respect to the internal dielectric layer (PIQ1) and covering an upper surface of the internal dielectric layer (IL5)
forming a second hardmask pattern (IF2) by etching the second hardmask layer with a second mask pattern (RP2)
forming a via hole (OP1) and trenches by etching the internal dielectric layer (PIQ1) with the second mask pattern and the second hardmask pattern (IF2)
forming an interconnection pattern (MF1) covering the via hole (OP1) and the trenches
wherein the interconnection pattern (MF1) includes a via part (MF1 in trench) covering the via hole, a pad part MF2) vertically overlapping the via part, and a line part (PD2) extending from the pad part
wherein the bottom surface of the pad part (MF2), the bottom surface of the line part, and a lateral surface of the via part (OP1) are in contact with the dielectric layer (PIQ1) (Figure 3)
Regarding claim 13, Usami discloses each of the first hardmask pattern and the second hardmask pattern includes a silicon oxide layer (paragraph 54), and a density of the second hardmask pattern is different from a density of the first hardmask pattern (paragraph 81).
Regarding claim 14, Usami discloses each of the first hardmask pattern and the second hardmask pattern includes a silicon oxide layer (paragraph 54), and a composition of silicon and oxygen in the second hardmask pattern is different from a composition of silicon and oxygen in the first hardmask pattern (paragraph 81).
Regarding claim 15, Usami discloses depositing a barrier/seed layer (SD) on the via hole (OP1) and the trenches, forming a metal layer (MF1) on the barrier/seed layer (SD), and performing a planarization process (PIQ2) on the barrier/seed layer (SD) and metal layer (MF1) (Figure 13).
Regarding claim 16, Usami discloses the trenches include a first trench (MF1) vertically overlapping the via hole (OP1) and a groove (BM3) extending from the first trench, wherein the pad part (MF2) fills the first trench (Figure 10, and the line part (BM3) fills the groove, and a level of a bottom surface of the first trench (MF1) is higher than a level of a bottom surface (BM2) of the groove (groove is below the trench penetrating IF1).
Regarding claim 17, Usami discloses removing the mask pattern by performing an ashing process after forming the via hole and the trenches by etching the dielectric layer (paragraph 111).
Regarding claim 19, Usami discloses the first dielectric layer includes at least one of polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers (paragraph 106).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Usami (US Publication No. 2018/0350760).
Regarding claim 4, Usami discloses the limitations as discussed in the rejection of claim 3 above. Usami describes a thickness of the first pad part (MF2) to be in the range of 5um to 10um and shows a level difference in element MF2 (paragraph 92; Figure 10). Usami is silent regarding a level difference between the bottom surface of the first pad part and the bottom surface of the line part is in a range of 0.3 um to 0.8 um. However, if would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the level difference between the bottom surface of the pad and line parts to be within this range to protect the device from parasitic capacitance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 8, Usami discloses the limitations as discussed in the rejection of claim 1 above. Usami describes a thickness of the first pad part (MF2) to be in the range of 5um to 10um and shows a level difference in element MF2 (paragraph 92; Figure 10). Usami is silent regarding a thickness of the first pad part is 1.1 times to 1.25 times a thickness of the line part. However, if would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the thickness difference to be within this range to protect the device from parasitic capacitance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 7 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Usami (US Publication No. 2018/0350760) in view of Sakata (US Publication No. 2008/0318409).
Regarding claim 7, Usami discloses the limitations as discussed in the rejection of claim 1 above. Usami does not disclose a top surface of the first pad part and a top surface of the line part are coplanar with a top surface of the first hardmask pattern. However, Sakata discloses a top surface of a wiring line (316) are coplanar with a top surface of a first hardmask (309a). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to form Usami’s top surface of the pad and line parts to be coplanar with the top surface of the first hard mask, as taught by Sakata, since it can protect diffusion of copper into the dielectric while maintaining a level wiring structure of interconnection (paragraph 22).
Regarding claim 18, Usami discloses the limitations as discussed in the rejection of claim 12 above. Usami does not disclose a top surface of the first pad part and a top surface of the line part are coplanar with a top surface of the first hardmask pattern. However, Sakata discloses a top surface of a wiring line (316) are coplanar with a top surface of a first hardmask (309a). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to form Usami’s top surface of the pad and line parts to be coplanar with the top surface of the first hard mask, as taught by Sakata, since it can protect diffusion of copper into the dielectric while maintaining a level wiring structure of interconnection (paragraph 22).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Usami (US Publication No. 2018/0350760) in view of Lin et al. (US Publication No. 2021/0193577).
Regarding claim 10, Usami discloses the limitations as discussed in the rejection of claim 1 above. Usami does not disclose the sidewall of a via part to have a rounded shape. However, Lin discloses a via (31) with a rounded shape (Figure 4). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the via part of Usami to include a rounded portion, as taught by Lin, since it can reduce process steps and improve alignment of the interconnection (paragraph 56).
Regarding claim 11, Lin discloses a slope of a sidewall of the via part (OP1) decreases as the sidewall approaches a top region of the via part from a bottom surface of the via part (Figure 4).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Usami (US Publication No. 2018/0350760) in view of Elsherbini (US Publication No. 2020/0364600).
Regarding claim 20, Usami discloses the limitations as discussed in the rejection of claim 12 above. Usami does not disclose the second interconnection pattern includes a first via part, a first pad part, and a first line part that are integrally connected to each other, the first pad part vertically overlaps the first via part, the first line part extends from the first pad part, a width of the first pad part is greater than a width of the first line part, and a level of a bottom surface of the first pad part is lower than a level of a bottom surface of the first line part. However, Elsherbini discloses a second interconnection pattern that includes a first via part, pad part, and line part connected to each other with a pad width greater than a line part and a pad part lower than a bottom surface of a line part (Figure 17D). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Usami to include a second interconnection as taught by Elsherbini, since it can minimize thermal stress by expanding interconnects farther apart while maintaining interconnection conductivity (paragraphs 66-67).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sabatini et al. (US Patent No. 8,026,608) discloses an interconnect (26) which is deeper than another interconnect and connected by a line (26) (Figure 5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/N.R.P/ 1/26/2026 Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897