Prosecution Insights
Last updated: April 18, 2026
Application No. 18/656,082

Flexible Interconnect Circuits And Methods Of Fabrication Thereof

Non-Final OA §102
Filed
May 06, 2024
Examiner
WILLIS, TREMESHA S
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cellink Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
679 granted / 873 resolved
+9.8% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
44 currently pending
Career history
917
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
31.6%
-8.4% vs TC avg
§102
49.7%
+9.7% vs TC avg
§112
16.8%
-23.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 873 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Coakley et al. (U.S. Patent Publication No. 2020/0137882). Regarding claim 1, in Figures 1C and 9A, Coakley discloses a flexible interconnect circuit assembly comprising: a flexible interconnect circuit (100; paragraph [0050]) comprising a first insulator layer (160, Figure 1C), a second insulator layer (170, Figure 1C), and conductive traces (132, Figure 9A), wherein: the first insulator layer and the second insulator layer define a first edge (102, paragraph [0059]; Figure 1C) and a second edge (right side edge 102; Figure 1C) of the flexible interconnect circuit, the conductive traces are positioned between the first insulator layer and the second insulator layer (Figure 9A), and the conductive traces are offset relative to each other between the first edge and the second edge in a portion of the flexible interconnect circuit (Figure 9A), the conductive traces are formed from a metal sheet (paragraph [0065]), and the conductive traces have a uniform thickness throughout a boundary of the flexible interconnect circuit (Figure 9A); and a molded seal (comprising110, 120; Figure 1C) enclosing the portion of the flexible interconnect circuit (first outer dielectric 110 directly interfaces second dielectric 120 at an edge, and forms edge 102, thereby causing more effective sealing, paragraph [0060]), wherein: the molded seal surrounds the first insulator layer and the second insulator layer in the portion of the flexible interconnect circuit (Figures 1C and 9A), and the molded seal is formed from a material selected from the group consisting of butyl (ethylene-butylene copolymers, paragraph [0103]), nitrile, styrene-butadiene rubber, polyvinyl chloride, vulcanized rubber, and ethylene propylene diene monomer rubber (modified propylene, paragraph [0101]; ethylene-butylene copolymers, paragraph [0103]). Regarding claim 2, Coakley discloses a first connector (915) and a second connector (915), wherein: the conductive traces interconnect connector terminals in the first connector and the second connector, and the portion of the flexible interconnect circuit enclosed by the molded seal is positioned between the first connector and the second connector (Figure 10I). Regarding claim 3, Coakley discloses an electronic control unit, wherein: the electronic control unit comprises an opening (925), the flexible interconnect circuit extends through the opening, the conductive traces are connected to the electronic control unit, and the molded seal is positioned at the opening of the electronic control unit filling the opening and preventing ingress into the electronic control unit thereby forming a compressible seal (Figure 10I). Regarding claim 4, Coakley discloses wherein the molded seal is configured to provide sealing as one or more of a door seal, a liftgate seal, a tailgate seal, a vehicle interior seal, and an engine bay seal (paragraph [0002]). Regarding claim 5, Coakley discloses wherein the molded seal has a lower melting temperature than the first insulator layer and the second insulator layer (paragraphs [0098], [0101], [0103]). Regarding claim 6, Coakley discloses wherein the molded seal directly interfaces each of the first insulator layer and the second insulator layer (Figures 1C, 9A). Regarding claim 7, Coakley discloses a protector collar (138, paragraph [0062]) positioned between the molded seal and each of the first insulator layer and the second insulator layer, wherein the protector collar is operable as a thermal barrier when forming the molded seal (Figures 1C, 9A). Regarding claim 8, Coakley discloses wherein the protector collar is further operable to align the flexible interconnect circuit while forming the molded seal (paragraph [0062]; Figures 1C, 9A). Regarding claim 9, Coakley discloses wherein the protector collar is formed from a material selected from the group consisting of nylon, a composite, steel, and aluminum (paragraph [0065]). Regarding claim 10, Coakley discloses a circuit carrier, wherein: the flexible interconnect circuit is positioned within the circuit carrier, and the flexible interconnect circuit is supported by the circuit carrier (Figure 1B). Regarding claim 11, Coakley discloses wherein the molded seal is positioned between the flexible interconnect circuit and the circuit carrier (Figure 1B). Regarding claim 12, Coakley discloses wherein the circuit carrier comprises a cover and a base structure, coupled to the cover and forming an enclosure around the flexible interconnect circuit extending through the circuit carrier (Figure 1B). Regarding claim 13, Coakley discloses wherein the conductive traces comprise aluminum (paragraph [0065]). Regarding claim 14, Coakley discloses wherein the first insulator layer and the second insulator layer comprises one or more polymer selected from the group consisting of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), ethyl vinyl acetate (EVA), polyethylene (PE), polyvinyl fluoride (PVF), polyamide (PA), and/or polyvinyl butyral (PVB) (paragraph [0098]). Regarding claim 15, in Figures 1C and 9A, Coakley discloses a method of forming flexible interconnect circuit assembly, the method comprising: providing a flexible interconnect circuit (100) comprising a first insulator layer (160, Figure 1C), a second insulator layer (170, Figure 1C), conductive traces (132, Figure 9A), wherein: the first insulator layer and the second insulator layer define a first edge (102, paragraph [0059]; Figure 1C) and a second edge (right side edge 102; Figure 1C) of the flexible interconnect circuit, the conductive traces are positioned between the first insulator layer and the second insulator layer (Figure 9A), and the conductive traces are offset relative to each other between the first edge and the second edge in a portion of the flexible interconnect circuit (Figure 9A), the conductive traces are formed from a metal sheet (paragraph [0065]), and the conductive traces have a uniform thickness throughout a boundary of the flexible interconnect circuit (Figure 9A); and forming a molded seal (comprising110, 120; Figure 1C) over the portion of the flexible interconnect circuit, wherein: the molded seal encloses the portion of the flexible interconnect circuit (first outer dielectric 110 directly interfaces second dielectric 120 at an edge, and forms edge 102, thereby causing more effective sealing, paragraph [0060]), the molded seal surrounds the first insulator layer and the second insulator layer in the portion of the flexible interconnect circuit (Figures 1C and 9A), and the molded seal is formed from a material selected from the group consisting of butyl (ethylene-butylene copolymers, paragraph [0103]), nitrile, styrene-butadiene rubber, polyvinyl chloride, vulcanized rubber, and ethylene propylene diene monomer rubber (modified propylene, paragraph [0101]; ethylene-butylene copolymers, paragraph [0103]). Regarding claim 16, Coakley discloses wherein: the flexible interconnect circuit comprises a support tab comprising openings (925, Figure 10I), forming the molded seal comprises positioning the flexible interconnect circuit into a molding cavity comprising pins, extending through the openings of the support tab, and the pins hold the flexible interconnect circuit in place while forming the molded seal, preventing deformation of the flexible interconnect circuit (Figures 10I -10J). Regarding claim 17, Coakley discloses attaching connectors (915, Figure 10I) to the flexible interconnect circuit, wherein: the conductive traces interconnect connector terminals in the connectors, and the portion of the flexible interconnect circuit enclosed by the molded seal is positioned between the connectors (Figure 10I). Regarding claim 18, Coakley discloses wherein the connectors are attached before forming the molded seal (Figures 10I -10J). Regarding claim 19, Coakley discloses wherein forming the molded seal is performed using one or more techniques selected from the group consisting of overmolding and insert molding (paragraphs [0101], [0103]). Regarding claim 20, Coakley discloses wherein forming the molded seal is performed using one or more techniques selected from the group consisting of injection molding, compression molding, transfer molding, single-shot molding, or multi-shot molding (paragraphs [0101], [0103]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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Prosecution Timeline

May 06, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §102
Mar 17, 2026
Examiner Interview Summary
Mar 17, 2026
Applicant Interview (Telephonic)
Mar 26, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.5%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 873 resolved cases by this examiner. Grant probability derived from career allow rate.

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