DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 06, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites the limitation “a MOSFET” in line 2. This limitation appears to be referring back to the original limitation recited in line 1 of claim 1. Thus, the limitation of line 2 should be amended to be “the MOSFET”. Appropriate correction is required.
Claim 1 is objected to because of the following informalities: Claim 1 recites the limitation “a gate leakage current” in line 3. This limitation appears to be referring back to the original limitation recited in line 1 of claim 1. Thus, the limitation of line 3 should be amended to be “the gate leakage current”. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: Claim 8 is claimed as a dependent claim of claim 1, however, the claim limitations of claim 8 further details the bypass switch which is original claimed in claim 7. Thus, the examiner believes that claim 8 should be amended to be a dependent claim of claim 7 and the examiner will interpret claim 8 as though it is a dependent claim of claim 7. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, this claim recites limitations that further details the bypass switch which the bypass switch is original claimed in claim 7, however, claim 8 is currently a dependent claim of claim 1. There is some confusion if the claim limitations of claim 8 are meant to be 1) as presented by the applicant or 2) is meant to be a dependent claim of claim 7 instead of claim 1. In the situation of the first case, the claim limitations need to be amended to clearly show that it is the first recitation of the limitations (antecedent basis) and are not tied to the limitations of claim 7. In the situation of the second case, claim 8 should be amended to be a dependent claim of claim 7 instead of claim 1. The examiner will interpret claim 8 as though it is a dependent claim of claim 7 because the claim limitations of claim 8 are further detailing the bypass switch.
Claim 9 is rejected for inheriting the deficiencies of claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang US2006/0012391 in view of Ramanan et al. US11145382 (called Ramanan hereinafter).
Regarding independent claim 1, Huang teaches an apparatus (Figs. 4b or 5b) for measuring a gate leakage current (Fig. 3b; para [0006 and 0024]) of a MOSFET (Fig. 5b; transistor 160), comprising:
a) a current mirror (Fig. 5b; current mirror 515) adapted to be connected to a gate (Fig. 5b; gate of transistor 160) of a MOSFET (Fig. 5b; transistor 160); an input current path (Fig. 5b; path from VDDP through transistors 520 and 160 to VSS) of the current mirror adapted to receive a gate leakage current of the MOSFET (para [0024]; current detector for extracting sub-threshold leakage current);
b) a gate driver (Fig. 5b; VDDP) adapted to generate a driving signal for the MOSFET (para [0024]).
Huang fails to teach c) a sensing resistor connected to the current mirror; the sensing resistor being located on an output current path of the current mirror.
Ramanan teaches c) a sensing resistor (Fig. 2; resistor 232) connected to the current mirror (Fig. 2; current mirror 208); the sensing resistor being located on an output current path of the current mirror (Fig. 2; output node 230; Column 4 lines 38-57).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention to modify the structure as described by Huang with the leakage current output and resistor as described by Ramanan for the purpose of reducing leakage currents to improve the read and write operations of non-volatile memories (Column 1 lines 12-31).
Regarding claim 4, Huang and Ramanan teach the apparatus of claim 1, Huang further teaches wherein the current mirror comprises a first transistor and a second transistor having their base connected together (Fig. 5b; transistors 520 and 525 have their bases/gates connected together at nodes 521 and 526); a collector of the first transistor adapted to be connected to the gate of the MOSFET (Fig. 5b; node 540 connected to the gate of transistor 160); a collector of the second transistor connected to the sensing resistor (Fig. 5b; bottom end of transistor 525 is the output with the sensing resistor of Ramanan).
Regarding claim 6, Huang and Ramanan teach the apparatus of claim 4, Huang further teaches wherein an emitter of the first transistor and an emitter of the second transistor are connected directly to the gate driver (Fig. 5b; the top of transistors 520 and 525 are connected to VDDP).
Regarding claim 13, Huang and Ramanan teach the apparatus of claim 1, Ramanan further teaches wherein one end of the sensing resistor is connected to the current mirror (Fig. 2; top of resistor 232), and another end of the of the sensing resistor is connected to a source of the MOSFET (Fig. 2; bottom of 232 connected to ground which is connected to node 216 of transistor 210 through reference array 218).
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang, in view of Ramanan and further in view of Bodano US2018/0059166.
Regarding claim 2, Huang and Ramanan teach the apparatus of claim 1, but fail to teach further comprises a turn-on resistor and a turn-off resistor, both of which are adapted to be connected to the gate of the MOSFET.
Bodano teaches a turn-on resistor and a turn-off resistor (Figs. 1b-d; resistor 104 and resistor 110 or 124), both of which are adapted to be connected to the gate of the MOSFET (Figs. 1b-d resistor 104 and resistor 110 or 124 are electrically connected to the gate of transistor 102).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention to modify the structure as described by Huang and Ramanan with the leakage current configuration of resistors as described by Bodano for the purpose of having resistors control the operational status of the transistors (para [0029 and 0031]).
Regarding claim 3, Huang, Ramanan and Bodano teach the apparatus of claim 2, Bodano further teaches wherein the turn-on resistor is located on the input current path of the current mirror (Figs. 1b-1d; resistor 110 or 124 is on the input current path connected to the current path for transistor 106); the turn-off resistor having one end adapted to be connected to the MOSFET (Figs. 1b-1d; bottom end of resistor 104 connected to transistor 102), and another end connected to the gate driver (Figs. 1b-1d; top end of resistor 104 connected to VIN).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang, in view of Ramanan and further in view of Forejtek et al. US2024/0072530 (called Forejtek hereinafter).
Regarding claim 5, Huang and Ramanan teach the apparatus of claim 4, Huang further teaches wherein the collector of the first transistor is connected directly to the base of thereof (Fig. 5b; node 540 connected to nodes 521 and 526).
Huang and Ramanan fail to teach the apparatus further comprising a diode that is connected between the collector and the base of the second transistor.
Forejtek teaches a diode that is connected between the collector and the base of the second transistor (Fig. 4; diode D1 in current mirror 410 is connected at the gate/base of transistor M3 and the collector/drain of transistor M3).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention to modify the structure as described by Huang and Ramanan with the diode as described by Forejtek for the purpose of protecting the gate/base terminals from high voltages (para [0041]).
Allowable Subject Matter
Claims 7 and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior arts of record taken alone or in combination fail to teach or suggest:
“further comprises a bypass switch connected in parallel to the current mirror; the bypass switch adapted to bypass the current mirror during a turn-on process of the MOSFET.”
Claims 8 and 9 would be indicated as allowable subject matter if claim 8 is amended to be a dependent claim of claim 7 as indicated by the examiner, in the 35 U.S.C. §112 rejection, above.
Regarding claim 10, the prior arts of record taken alone or in combination fail to teach or suggest:
“further comprises a discharging circuit connected to the current mirror; the discharging circuit adapted to shorten a timer period required for the first transistor and the second transistor to transit from a saturation mode to a linear mode.”
Claims 11 and 12 are indicated as allowable subject matter for depending on claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lih et al. discloses “Keeper circuits having dynamic leakage compensation” (see US2006/0214695)
Sicard et al. discloses “MOS transistor drain-to-gate leakage protection circuit and method therefor” (see US2012/0326690)
Okandan et al. discloses “Method and apparatus for measuring gate leakage current in an integrated circuit” (see US6348806)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID B FREDERIKSEN whose telephone number is (571)272-8152. The examiner can normally be reached M-F 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID B FREDERIKSEN/Examiner, Art Unit 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858