Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities: The claim reads, “the plurality of contact pads included the metal pad”. It is believed the claim ought to read, “the plurality of contact pads includes the metal pad”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
Claim(s) 1-4, 8-10, 12-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai (USPGPUB 20240413187, hereinafter “Arai”) in view of Jang et al (USPGPUB 20220059596, hereinafter “Jang”).
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Regarding Claim 1, Arai teaches a stacked semiconductor device, comprising: a first die (210) including a first semiconductor substrate (SS1) and a first interconnect stack (IS1); a second die (220) including a second semiconductor substrate (SS2) and a second interconnect stack (IS2), wherein the first interconnect stack (IS1) and the second interconnect stack (IS2) are disposed between the first semiconductor substrate (SS1) and the second semiconductor substrate (SS2); a plurality of first bonding pads (215) disposed within the first interconnect stack (IS1) and a plurality of second bonding pads (228) disposed within the second interconnect stack (IS2), wherein the plurality of first bonding pads contact (first bonding pads 215 are seen in contact with second bonding pads 228) the plurality of second bonding pads (228) at a bonding interface (B) to form a plurality of bonding connections (first bonding pads 215 and second bonding pads 228 are seen joined at bonding interface B, forming bonding connections between the dies 210 and 220), the plurality of bonding connections including rail connections (RC; pads RC as seen in the annotated Fig. 1 of Arai are connected to metal pad 214) and signal connections (SC; connections SC are seen as signal connections as they are seen coupled to local wiring structures on the right-hand region of the semiconductor substrate SS1); and a metal pad (214) embedded in (metal pad 214 is seen embedded in the first semiconductor substrate) the first semiconductor substrate (SS1), wherein the metal pad (214) is coupled to a first rail connection (leftmost RC, hereinafter “RC1”) included in the rail connections (RC),
Arai is silent with regards to a device wherein the metal pad extends laterally between a first pair of the plurality of bonding connections when the stacked semiconductor device is viewed from a plan view.
Jang (Fig. 7) teaches a device wherein the metal pad extends laterally between (the array of bonding connections 21a are arranged such that the metal pad 214 would be seen extending laterally between them in an embodiment of Arai in view of Jang) a first pair of the plurality of bonding connections (21a) when the stacked semiconductor device is viewed from a plan view (Fig. 7 is a plan view, and the pad would be seen extending between some of the bonding connections 21a when located from this view).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the connection scheme of Jang into the device of Arai in order to arrive at the expected result of creating a device with more connections, allowing for more secure and efficient data transfer between electronics with reasonable expectation of success.
Regarding Claim 2, Arai in view of Jang teaches the stacked semiconductor device of claim 1, further comprising: a second rail connection (Arai RC, rightmost) included in the rail connections (RC), the second rail connection (RC, rightmost) coupled to (the second rail connection is seen electrically coupled and in direct contact with the ) the metal pad (Arai 214); and a first metal wire (227) coupled to the first rail connection (RC, leftmost) and the second rail connection (RC, rightmost), wherein the first metal wire (Arai 227) is disposed within (first metal wire 227 is seen disposed within the second interconnect stack IS2) the second interconnect stack (IS2), wherein the metal pad (214) and the first metal wire (227) respectively provide a first conductive path (conductive path including the first and second rail connections RC and the metal pad 214) and a second conductive path (conductive path including first and second rail connections RC and first metal wire 227) coupled in parallel (as seen in Fig. 1, the first metal wire 227 and the metal plate 214 are seen placed at ends of opposite conductive paths including rail connections RC) through the first rail connection (RC, leftmost) and the second rail connection (RC, rightmost), wherein the first metal wire (227) and the metal pad (214) each extend laterally from (first metal wire 227 and metal pad 214 are seen extending laterally from first rail connection RC, leftmost to second rail connection RC, rightmost) the first rail connection (RC, leftmost) to the second rail connection (RC, rightmost).
Regarding Claim 3, Arai in view of Jang teaches the stacked semiconductor device of claim 2, wherein the first metal wire (Arai 227) extends laterally between (the array of bonding connections 21a are arranged such that the first metal wire 227 would be seen extending laterally between them in an embodiment of Arai in view of Jang) the first pair of the plurality of bonding connections (Jang 21a) when viewed from the plan view, wherein the metal pad (Arai 214) has a first width (horizontal width in the x-direction, as seen in Fig. of metal pad 214 of Arai) and the first metal wire (227) has a second width (horizontal width in the x-direction, as seen in Fig. of first metal wire 227 of Arai), wherein the first width is greater than (horizontal width of metal pad 214 of Arai is seen greater than the horizontal width of first metal wire 227 of Arai) the second width.
Regarding Claim 4, Arai in view of Jang teaches the stacked semiconductor device of claim 2, wherein the metal pad (Arai 214) and the first metal wire (Arai 227) are arranged such that the metal pad (Arai 214) covers, at least in part (from a plan view, i.e. a top-down view, the metal pad 214 would be covering the metal wire 227), the first metal wire (227) when viewed from the plan view, and wherein the first pair of the plurality of bonding connections are included in the signal connections (an embodiment where the bonding connections are signal connections, as opposed to power or rail connections, would be obvious to a person of ordinary skill in the art, and would be achieved due to obvious modifications that are device-specific).
Regarding Claim 8, Arai in view of Jang teaches the stacked semiconductor device of claim 2, wherein the first conductive path (conductive path including the first and second rail connections RC and the metal pad 214) and the second conductive path (conductive path including first and second rail connections RC and first metal wire 227) extend from the first rail connection (RC, leftmost) to the second rail connection (RC, rightmost) a first distance along a first direction (x-direction of Arai Fig. 1), and wherein individual bonding connections included in the first pair of the plurality of bonding connections are separated by a second distance extending along a second direction perpendicular to the first direction when viewed from the plan view (the bonding connections 21a of Jang would be understood by a person of ordinary skill in the art to be aligned in an into-and-out-page direction of Fig. 1 of Arai, corresponding similarly to a direction perpendicular to line A-A’ as seen in Fig. 1 of Jang).
Regarding Claim 9, Arai in view of Jang teaches the stacked semiconductor device of claim 1, further comprising an isolation trench (within the first semiconductor substrate SS1, there is a trench seen formed, filled with isolation material 212, and the isolation material 212 is seen surrounding metal pad 214) formed within the first semiconductor substrate (SS1), wherein the metal pad (214) is disposed within the isolation trench (212) , and wherein the isolation trench is filled with an isolation material (212) surrounding the metal pad (214) to electrically isolate the metal pad from a substrate material (211) of the first semiconductor substrate (SS1).
Regarding Claim 10, Arai in view of Jang teaches the stacked semiconductor device of claim 9, wherein the isolation trench includes an opening (Arai 213) extending through (Arai opening 213 is seen extending through the isolation material 212) the isolation material (212) to expose a surface of (upper surface of metal pad 214 is seen exposed by the opening 213) the metal pad (214), and wherein the opening defines a contact window (Arai [0093], “an opening 213 for a pad penetrates up to a wiring 227 for external connection of a logic substrate 220”) for the metal pad to enable an external connection to the metal pad (214).
Regarding Claim 12, Arai in view of Jang teaches the stacked semiconductor device of claim 1, wherein the first die (Arai 210) includes a plurality of photodiodes (Jang [0003], “A CIS includes a plurality of pixels that are two-dimensionally arranged. Each of the pixels includes a photodiode (PD). The photodiode converts incident light into an electrical signal”; Jang [0024], “The second conductivity type may be, for example, an N-type. The N-type dopants in the photoelectric conversion portion PD form a PN junction with the P-type dopants in a region of the first substrate 1 adjacent to the photoelectric conversion portion PD, and thus a photodiode is provided”) disposed within the first semiconductor substrate (Jang 1) and arranged in rows and columns to form a pixel cell array (Fig. 1 of Jang shows an array of pixels UP), wherein the first die (Arai 210) further includes a plurality of contact pads laterally surrounding (contact pads 29c and 34 are seen in Fig. 1 of Jang laterally surrounding the pixel cell array of pixels UP) the pixel cell array (array of pixel cells UP) when viewed from the plan view, and wherein the plurality of contact pads includes the metal pad (34 of Jang).
Regarding Claim 13, Arai in view of Jang teaches (Arai Fig. 1) the stacked semiconductor device of claim 1, wherein the second die (Arai 220) includes circuitry disposed in or on the second semiconductor substrate (Arai SS2), and wherein the metal pad (Arai 214) is coupled to the circuitry (Arai 225) through the first rail connection (Arai RC, leftmost) to provide (the metal pad 214 of Arai and second circuitry 225 of Arai are seen forming a conductive pathway, which includes first metal wire 227 of Arai; Arai [0048], “The wiring 214 for external connection is a wiring for electrically connecting the pixel sensor substrate 210 and external parts (such as the logic substrate 220, and a test apparatus) to each other, and an aluminum wiring or the like is used”; a supply voltage would be an inherent property of the externally connecting metal pad 214) a supply voltage to the circuitry (225).
Regarding Claim 14, the stacked semiconductor device of claim 1, wherein the plurality of bonding connections (215 and 228 of Arai) include metal-metal bonds associated with (Arai [0048], “The pixel sensor substrate 210 is electrically connected to the logic substrate 220 via the wiring 214 for external connection and the connection part 215. As a connection method of these substrates, for example, Cu—Cu connection is used.”) the plurality of first bonding pads (215) contacting the plurality of second bonding pads (228), wherein individual bonding pads included in the plurality of first bonding pads (215) and the plurality of second bonding pads (228) are arranged in rows and columns to form an array of bonding connections collectively corresponding to the plurality of bonding connections (bonding connections RC and SC of Arai), wherein the first pair of bonding connections are in a same column included in the columns, wherein the first pair of bonding connections are in different rows included in the rows (the checkerboard shape of the bonding pads would be seen as in Fig. 1 of Jang, wherein the bonding pads are seen located on the borders of the different pixels UP in the pixel cell array), and wherein the metal pad (214) extends between (the array of bonding connections 21a of Jang are arranged such that the metal pad 214 would be seen extending laterally between them in an embodiment of Arai in view of Jang) the different rows when viewed from the plan view (top view as seen in Jang Fig. 1).
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Regarding Claim 15, Arai teaches an image sensor, comprising: a first die (210) including a first interconnect stack (IS1) and a first semiconductor substrate; a second die (220) including a second interconnect stack (IS2) and a second semiconductor substrate (SS2) having integrated circuitry (IC), wherein the first interconnect stack (IS1) and the second interconnect stack (IS2) are disposed between (SS2) the first semiconductor substrate (SS1) and the second semiconductor substrate (SS2); a plurality of first bonding pads (215) disposed within the first interconnect stack (IS1) and a plurality of second bonding pads (228) disposed within the second interconnect stack (IS2), wherein the plurality of first bonding pads (215) contact (first bonding pads 215 are seen in contact with second bonding pads 228) the plurality of second bonding pads (228) at a bonding interface (B) to form a plurality of bonding connections (RC and SC), the plurality of bonding connections (RC and SC ) including rail connections (RC) and signal connections (SC); and a metal pad (214) embedded in the first semiconductor substrate (SS1), wherein the metal pad (214) is coupled to (metal pad 214 is seen in contact with, and therefore electrically coupled to, the first rail connection RC, leftmost) a first rail connection (RC, leftmost) included in the rail connections (RC).
Arai is silent with regards to a plurality of photodiodes disposed within the first semiconductor substrate to form a pixel cell array and wherein the metal pad extends laterally between a first pair of the plurality of bonding connections when the image sensor is viewed from a plan view.
Jang teaches (Figs. 1 and 2) a plurality of photodiodes (Jang [0003], “A CIS includes a plurality of pixels that are two-dimensionally arranged. Each of the pixels includes a photodiode (PD). The photodiode converts incident light into an electrical signal”; Jang [0024], “The second conductivity type may be, for example, an N-type. The N-type dopants in the photoelectric conversion portion PD form a PN junction with the P-type dopants in a region of the first substrate 1 adjacent to the photoelectric conversion portion PD, and thus a photodiode is provided”) disposed within the first semiconductor substrate to form a pixel cell array (array of pixel cells UP) and wherein the metal pad (34) extends laterally between a first pair of the plurality of bonding connections (the array of bonding connections 21a are arranged such that the metal pad 214 would be seen extending laterally between them in an embodiment of Arai in view of Jang) when the image sensor is viewed from a plan view (top-down view, such as that seen in Fig. 1 of Jang).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the connection scheme of Jang into the device of Arai in order to arrive at the expected result of creating a device with more connections, allowing for more secure and efficient data transfer between electronics with reasonable expectation of success.
Regarding Claim 16, Arai in view of Jang teaches the image sensor of claim 15, further comprising a plurality of contact pads laterally surrounding (contact pads 29c of and 34 are seen in Fig. 1 of Jang laterally surrounding the pixel cell array of pixels UP) the pixel cell array (array of pixel cells UP of Jang) when viewed from the plan view, and wherein the plurality of contact pads includes the metal pad (34 of Jang).
Regarding Claim 17, Arai in view of Jang teaches (Arai Fig. 1) the image sensor of claim 15, further comprising: a second rail connection (Arai RC, rightmost) included in the rail connections (Arai RC), the second rail (RC, rightmost) connection coupled to the metal pad (Arai 214); and a first metal wire (227) coupled to the first rail connection (RC, leftmost) and the second rail connection (RC, rightmost), wherein the first metal wire (227) is disposed within the second interconnect stack (IS2), wherein the metal pad (Arai 214) and the first metal wire (Arai 227) respectively provide a first conductive path and a second conductive path coupled in parallel, (as seen in Fig. 1, the first metal wire 227 and the metal plate 214 are seen placed at ends of opposite conductive paths including rail connections RC) each extending from the first rail connection (RC, leftmost) to the second rail connection (RC, rightmost).
Regarding Claim 19, Arai in view of Jang teaches the image sensor of claim 17, wherein the first conductive path and the second conductive path extending from the first rail connection (RC, leftmost) to the second rail connection (RC, rightmost) is along a first direction, and wherein individual bonding connections included in the first pair of the plurality of bonding connections are separated by a distance extending along a second direction perpendicular to the second direction when viewed from the plan view (the bonding connections 21a of Jang would be understood by a person of ordinary skill in the art to be aligned in an into-and-out-page direction of Fig. 1 of Arai, corresponding similarly to a direction perpendicular to line A-A’ as seen in Fig. 1 of Jang).
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Allowable Subject Matter
Claims 5-7, 11,18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Regarding Claim 5, the closest available references, that of Arai and Jang, alone or in any reasonable combination, fails to teach the limitation, “a second metal wire coupled to a third rail connection and a fourth rail connection included in the rail connections”. Claim 6 is dependent upon Claim 5. (third and fourth rail connections are not seen in any other available references in such a way that they would be motivated for inclusion into an embodiment of the above independent claim(s) ).
Regarding Claim 7, the closest available references, that of Arai and Jang, alone or in any reasonable combination, fails to teach the limitation, “the second interconnect stack includes a plurality of metal layers including a distal metal layer disposed closer to the bonding interface than any other metal layer included in the plurality of metal layers, and wherein the first metal wire is included in the distal metal layer” (The second interconnect stack, being one of two interconnect stacks between semiconductor substrates which embed the metal pad, do not, and are not reasonably able to be motivated to, include metal layers or circuit wiring).
Regarding Claim 11, the closest available references, that of Arai and Jang, alone or in any reasonable combination, fails to teach the limitation, “the first interconnect stack includes a plurality of metal layers including a proximal metal layer disposed closer to the first semiconductor substrate any other metal layer included in the plurality of metal layers” (The second interconnect stack, being one of two interconnect stacks between semiconductor substrates which embed the metal pad, do not, and are not reasonably able to be motivated to, include wiring).
Regarding Claim 18, the closest available references, that of Jang and Arai, alone or in any reasonable combination, fails to teach the combination, “The image sensor of claim 17, further comprising: a second metal wire coupled to a third rail connection and a fourth rail connection included in the rail connections”. (third and fourth rail connections are not seen in any other available references in such a way that they would be motivated for inclusion into an embodiment of the above independent claim(s) ).
Regarding Claim 20, the closest available references, that of Arai in view of Jang, alone or in any combination, fails to teach the limitation, “the isolation trench is filled with an isolation material surrounding the metal pad to electrically isolate the metal pad from the first semiconductor substrate” As opposed to in claim 9 above, claim 20 teaches the first semiconductor substrate, in its entirety, being isolated from the metal pad. This is not taught by either of the above references or reasonably incorporated by any other available prior art.
Conclusion
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/V.J.L./Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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