DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 2-6, 8-13 and 15-21 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Ameti (US 5,408,628).
Consider claim 2, Ameti et al. discloses a memory controller for controlling a first memory device having an array of memory cells for storing data, the memory controller comprising: a command/address interface to transmit a connectivity read command to the first memory device over a command/address link; a data interface to receive a bit pattern over a data link from the first memory device in response to the connectivity read command; and connectivity discovery logic to detect a connectivity state between the memory controller and the first memory device based on the bit pattern received at the data interface, wherein the connectivity state indicates a detected mapping of at least one data line of the data interface with at least one data line of the memory device that was used in communicating the bit pattern from respective stored bit locations in the memory device to the data interface of the memory controller, and to configure the memory controller for communicating with the first memory device based on the connectivity state (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses sending commands using a predetermined length and in the process of accessing the memory, some locations in the memory may be bad (connectivity issues) which will cause the predetermined length to be adjusted, using masking (bit pattern), based on condition of the memory and this new length will be used. The bit masking is a mapping that indicates connectivity states of each bit. The mask has 1’s placed in it where a failed bit location is along with interfaces/buses.).
Consider claim 3, Ameti et al. discloses the memory controller of claim 2, wherein transmitting the connectivity read command includes transmitting a first bit pattern to the first memory device, wherein the bit pattern received by the memory controller comprises a second bit pattern, wherein the connectivity discovery logic determines the connectivity state based in part on a predefined mapping of the second bit pattern to the first bit pattern (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses using masking to provide connectivity without accessing bad memory locations.).
Consider claim 4, Ameti et al. discloses the memory controller of claim 2, wherein the bit pattern received from the first memory device has a single data bit set to a first logic value and remaining data bits set to a second logic value different than the first logic value (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. the mask has 1’s placed in it where a failed bit location is.).
Consider claim 5, Ameti et al. discloses the memory controller of claim 2, wherein transmitting the connectivity read command includes transmitting a predetermined sequence to the first memory device, wherein for each bit pattern in the predetermined sequence transmitted to the first memory device, the memory controller receives a unique bit pattern to indicate connectivity of a unique data pin of the memory device (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses sending commands using a predetermined length and in the process of accessing the memory, some locations in the memory may be bad (connectivity issues) which will cause the predetermined length to be adjusted, using masking (bit pattern), based on condition of the memory and this new length will be used.).
Consider claim 6, Ameti et al. discloses the memory controller of claim 2, wherein the connectivity discovery logic is configured to automatically select between at least a first data interface configuration and a second data interface configuration upon initialization (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses that interfaces/buses can also be masked out. For claim 12, masking out an interface/bus is considered a mode change.).
Consider claim 8, Ameti et al. discloses the memory controller of claim 2, wherein the command/address link and the data interface are further coupled to a second memory device, and wherein the memory controller is configured to communicate with the first memory device via a first subset of memory controller data pins of the data interface and to communicate with the second memory device via a second subset of memory controller data pins of the data interface (Summary of invention, Col. 3 lines 14-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses a memory array with multiple memories.).
Claims 9-13 and 15 are the method claims to controller claims 2-6 and 8 and are rejected in the same manner using the same rationale.
Consider claim 16, Ameti et al. discloses a memory controller for controlling a memory device having an array of memory cells for storing data, the memory controller comprising: a command/address interface to transmit a predetermined bit sequence to the memory device over a command/address link; a data interface to receive a plurality of bit patterns from the memory device, each bit pattern received corresponding to a subset of bit values from the predetermined bit sequence, each bit pattern having a single bit representing a first logic state to indicate connectivity of a unique data pin of the memory device and remaining bits other than the single bit in the bit pattern representing a second logic state that is different from the first logic state; and a circuit to detect a connectivity configuration of each pin of a data interface of the memory device based on the plurality of bit patterns received by the data interface of the memory controller (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses sending commands using a predetermined length and in the process of accessing the memory, some locations in the memory may be bad (connectivity issues) which will cause the predetermined length to be adjusted, using masking (bit pattern), based on condition of the memory and this new length will be used.).
Consider claim 17, Ameti et al. discloses the memory controller of claim 16, wherein the command/address interface is to transmit a connectivity read command in association with the predetermined bit sequence, wherein the circuit is to determine the connectivity configuration based in part on a predefined mapping of the transmitted predetermined bit sequence to the plurality of bit patterns received (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses using masking to provide connectivity without accessing bad memory locations.).
Consider claim 18, Ameti et al. discloses the memory controller of claim 16, wherein the command/address interface is to transmit the predetermined bit sequence upon initialization of the memory device (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses that interfaces/buses and failed byte locations can be masked out, while the system is running.).
Consider claim 19, Ameti et al. discloses the memory controller of claim 16, wherein the circuit is configured to select an operating mode of the memory controller between a first mode in which the memory device is coupled to the memory controller by a first data interface configuration, and a second mode in which the memory device is coupled to the memory controller by a second data interface configuration (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses that interfaces/buses can also be masked out. For claim 12, masking out an interface/bus is considered a mode change.).
Consider claim 20, Ameti et al. discloses the memory controller of claim 16, wherein for each bit pattern in the predetermined bit sequence transmitted to the memory device, the memory controller receives a unique bit pattern to indicate connectivity of a different unique data pin of the memory device (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses sending commands using a predetermined length and in the process of accessing the memory, some locations in the memory may be bad (connectivity issues) which will cause the predetermined length to be adjusted, using masking (bit pattern), based on condition of the memory and this new length will be used.).
Consider claim 21, Ameti et al. discloses the memory controller of claim 16, further comprising a plurality of data pins, wherein each of the bit patterns includes one bit in the first logic state and remaining bits in a second logic state such to individually determine a connectivity of each data pin of the memory controller and respective memory device data pins of the memory device (Summary of invention, Col. 3 lines 27-44, Col. 4 lines 1-6, Col. 7 lines 32-38 and 51-67, Col. 8 lines 24-29, Col. 9 lines 23-63, Ameti et al. discloses the mask has 1’s placed in it where a failed bit location is along with interfaces/buses.).
Response to Arguments
Applicant's arguments filed 10/31/2025 have been fully considered but they are not persuasive.
The applicant argues, with respect to the independent claims, that Ameti does not detect a connectivity state or mapping and rather only detects bad memory locations. However, the detection of bad memory locations and masking/altering mappings to avoid them are considered detecting connectivity states and address mappings.
Further, with respect to claim 16, the applicant argues that Ameti discloses identifying failed memory locations rather than a “connectivity configuration,” as claimed. For example, Ameti does not disclose receiving any “bit pattern...to indicate connectivity of a unique data pin of the memory device,” as claimed. Moreover, Ameti does not disclose any specific bit pattern including “a single bit representing a first logic state,” and “remaining bits ... representing a second logic state that is different from the first logic state,” as claimed. Moreover, Ameti provides no suggestion that such a bit pattern would be operational for the purpose of detecting failed memory locations (which differs from the claimed circuit for determining of a “connectivity configuration.”).
However, as rejected, the determining of bad memory locations and masking bits along data paths is considered to be identifying failed memory locations by providing a connection configuration that will work. Further a first bit will have a first logic state (logic value) and a sequence of other remaining bits with have a second logic state (logic value). For example, a bit of state “1” with have a value of 1 and a bit state of “1111111” with have a logic value of 127, these values are different as per the new limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2136