DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on May 06, 2024 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: NON-VOLATILE MEMORY DEVICE COMPRISING A SINGLE CRYSTALLINE SILICON AND POLYSILICON CHANNEL AND THE METHOD OF MANUFACTURING THE SAME.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on June 20, 2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang (US 2022/0416052 A1).
Claim 1, Kang discloses a method of manufacturing a memory device (semiconductor device 100 is a memory device, hereinafter, memory device 100, [0028] and [0088], Figs. 10-17), the method comprising:
forming a stack structure (first horizontal sacrificial layers 111, second horizontal sacrificial layers 112, second horizontal conductive layer 104, sacrificial insulating layers 118 and interlayer insulating layers 120 form a stack structure, hereinafter, stack structure 118/120, [0089], Fig. 10) including first material layers (interlayer insulating layers 120 are first material layers, hereinafter, first material layers 120, [0089], Fig. 10) alternately stacked with second material layers (first material layers 120 are alternately stacked with sacrificial insulating layers 118, which are second material layers, hereinafter, second material layers 118, [0089], Fig. 10);
forming a channel layer (channel layer 140/140e is formed, [0099], Figs. 12A and 12B) including amorphous silicon in an opening (channel layer 140/140e includes amorphous silicon in the channel holes CHH/CHe which is an opening, hereinafter, opening CHH/CHe, [0101], Figs. 12A and 12B) extending through the stack structure 118/120 (channel layer 140/140e includes amorphous silicon in an opening CHH extending through the stack structure 118/120, [0101], Figs. 12A and 12B);
converting a first part of the channel layer (upper region SR2 of the channel layer 140/140e is a first part of the channel layer, hereinafter, first part SR2 of the channel layer 140/140e, [0044], Fig. 4) into single crystalline silicon (first part SR2 of the channel layer 140/140e is converted to single crystalline silicon, [0101], Fig. 13A and 13B);
doping the first part SR2 of the channel layer 140/140e with a conductive material (first part SR2 of the channel layer 140/140e may be doped, [0101], Figs. 12A and 12B);
doping a second part of the channel layer (lower region SR1 of the channel layer 140/140e is a second part of the channel layer 140/140e, hereinafter, second part SR1 of the channel layer 140/140e, [0044], Fig. 4) with the conductive material (second part SR1 of the channel layer 140/140e may be doped, [0044], Fig. 4), wherein the second part is different from the first part (channel layer 140/140e may be doped, wherein the second part SR1 of the channel layer 140/140e is different from the first part SR2 of the channel layer 140/140e (i.e. single crystal silicon vs. polycrystalline silicon crystalline grain structure), [0044], Fig. 4); and
converting the second part SR1 of the channel layer 140/140e into polycrystalline silicon using the conductive material (second part SR1 of the channel layer 140/140e is converted into polycrystalline silicon using the conductive material (i.e. conductive material for metal induced lateral crystallization (MILC)), [0045], Fig. 4).
Claim 2, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 1.
Kang discloses wherein the forming the channel layer 140/140e comprises:
forming the opening CHH/CHe extending through the stack structure 118/120 (opening CHH/CHe extending through the stack structure 118/120 is formed, [0093], Fig. 11A);
forming a memory layer (gate dielectric layer 150 includes blocking layer 152, charge storage layer 154, and tunneling layer 156 and is a memory layer, hereinafter, memory layer 150, [0050], Fig. 12B) on an inner surface of the stack structure 118/120 surrounding the opening CHH/CHe (memory layer 150 is formed on an inner surface of the stack structure 118/120 surrounding the opening CHH/CHe (i.e. blocking layer 152), [0050], Fig. 12B) and an outer surface of the stack structure 118/120 (memory layer 150 is formed on an outer surface of the stack structure 118/120 (i.e. tunneling layer 156), [0050], Fig. 12B); and
forming the channel layer 140/140e on the memory layer 150 (channel layer 140/140e is formed on the memory layer 150, [0050], Fig. 12B).
Claim 3, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 2.
Kang discloses wherein, during the forming of the channel layer 140/140e on the memory layer 150, the channel layer 140/140e is formed on the inner surface of the stack structure 118/120 surrounding the opening CHH/CHe and the outer surface of the stack structure 118/120 (channel layer 140/140e is formed on the inner surface of the stack structure 118/120 surrounding the opening CHH/CHe and the outer surface of the stack structure 118/120, [0067], Figs. 6B and 12B), wherein the outer surface of the stack structure 118/120 and the inner surface of the stack structure 118/120 are on consecutive sides of the stack structure 118/120 (outer surface of the stack structure 118/120 and the inner surface of the stack structure 118/120 are on consecutive sides of the stack structure 118/120, [0067], Figs. 6B and 12B).
Claim 4, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 1.
Kang discloses wherein converting the first part SR2 into the single crystalline silicon comprises:
forming a cover layer (channel buried insulating layer 155 is a cover layer, hereinafter, cover layer 155, [0067], Figs. 6B and 12B) such that a portion of an inner surface of the channel layer 140/140e is exposed through a recess (cover layer 155 is formed such that a portion of an inner surface of the channel layer 140/140e is exposed through a recess, [0067], Figs. 6B and 12B);
forming a conductive layer (metal silicide layer 160 is a conductive layer, hereinafter, conductive layer 160, [0067], Figs. 6B and 12B) on the exposed inner surface of the channel layer 140/140e (conductive layer 160 is formed on the exposed inner surface of the channel layer 140/140e, [0067], Figs. 6B and 12B); and
converting the first part SR2 into the single crystalline silicon using the conductive layer 160 (first part SR2 of the channel layer 140/140e is converted into single crystalline silicon using the conductive layer 160 (i.e. conductive material for metal induced lateral crystallization (MILC)), [0045], Fig. 4).
Claim 5, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 4.
Kang discloses wherein forming the cover layer 155 comprises:
forming a preliminary cover layer 155 inside the channel layer 140/140e (forming the cover layer 155 comprises forming a preliminary cover layer 155 inside the channel layer 140/140e, as before the cover layer 155 is complete, it may be referred to as a preliminary cover layer 155, [0068], Fig. 6B); and
forming the recess by removing a portion of the preliminary cover layer (a recess is formed when a portion of the preliminary cover layer 155 is removed during processing, [0068], Fig. 6B);
wherein the portion of the inner surface of the channel layer 140/140e is exposed through the recess (a portion of the inner surface of the channel layer 140/140e is exposed through the recess, [0068], Figs. 6B and 12B).
Claim 6, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 4.
Kang discloses wherein converting the first part SR2 into single crystalline silicon using the conductive layer 160 comprises:
converting the conductive layer 160 into a silicide layer using a first heat treatment (first part SR2 of the channel layer 140/140e is converted into single crystalline silicon by converting the conductive layer 160 into a silicide layer 160 using a first heat treatment (i.e. conductive material for metal induced lateral crystallization (MILC)), [0045], Fig. 4); and
inducing crystallization of the first part SR2 by using the silicide layer 160 during a second heat treatment (crystallization of the first part SR2 is induced by using the silicide layer 160 during a second heat treatment, [0046], Figs. 6B and 12B).
Claim 7, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 6.
Kang discloses wherein the silicide layer 160 moves toward the cover layer 155 during the second heat treatment (silicide layer 160 moves toward the cover layer 155 during the second heat treatment, [0046], Figs. 6B and 12B).
Claim 8, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 4.
Kang discloses wherein a first surface of the cover layer 155 is adjacent to the recess, and the first surface of the cover layer 155 is disposed between the recess and a first end of the first part SR2 of the channel layer 140/140e as formed during converting of the first part SR2 into the single crystalline silicon using the conductive layer 160 (first surface of the cover layer 155 is adjacent to the recess, and the first surface of the cover layer 155 is disposed between the recess and a first end of the first part SR2 of the channel layer 140/140e as formed during converting of the first part SR2 into the single crystalline silicon using the conductive layer 160, [0046], Figs. 6B and 12B).
Claim 9, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 1.
Kang discloses wherein doping the first part SR2 with the conductive material and doping the second part SR1 with the conductive material are performed simultaneously (doping the first part SR2 with the conductive material and doping the second part SR1 with the conductive material may be performed simultaneously, [0044], Figs. 6B and 12B).
Claim 10, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 1.
Kang discloses wherein converting the second part SR1 comprises using a third heat treatment (converting the second part SR1 comprises using a third heat treatment (i.e. recrystallization by high temperature), [0045], Figs. 6B and 12B).
Claim 11, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 1.
Kang discloses wherein a first end of the second part SR1 (upper end of second region CR2 is a first end of the second part, hereinafter, first end CR2 of the second part SR1, [0045], Fig. 4) is formed adjacent to a first end of the first part SR2 (first end CR2 of the second part SR1 is formed adjacent to the bottom end of third region CR3 and is a first end CR3 of the first part SR2, [0045], Fig. 4).
Claim 12, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 1.
Kang discloses further comprising, after converting the second part SR1 into polycrystalline silicon, removing the conductive material from the channel layer (conductive material is removed from adjacent to the second part SR1 after converting the second part SR1 into polycrystalline silicon, [0116], Figs. 6B, 12B, and 16A).
Claim 13, Kang discloses a memory device (semiconductor device 100 is a memory device, hereinafter, memory device 100, [0028] and [0088], Figs. 10-17), comprising:
a stack structure (first horizontal sacrificial layers 111, second horizontal sacrificial layers 112, second horizontal conductive layer 104, sacrificial insulating layers 118 and interlayer insulating layers 120 form a stack structure, hereinafter, stack structure 118/120, [0089], Fig. 10); and
a channel layer (channel layer 140/140e is formed, [0099], Figs. 12A and 12B) formed in an opening (channel layer 140/140e includes amorphous silicon in the channel holes CHH/CHe which is an opening, hereinafter, opening CHH/CHe, [0101], Figs. 12A and 12B) extending through the stack structure 118/120 (channel layer 140/140e includes amorphous silicon in an opening CHH extending through the stack structure 118/120, [0101], Figs. 12A and 12B),
wherein the channel layer 140/140e includes a first part (upper region SR2 of the channel layer 140/140e is a first part of the channel layer, hereinafter, first part SR2 of the channel layer 140/140e, [0044], Fig. 4) including single crystalline silicon (first part SR2 of the channel layer 140/140e is converted to single crystalline silicon, [0101], Fig. 13A and 13B) and a second part (lower region SR1 of the channel layer 140/140e is a second part of the channel layer 140/140e, hereinafter, second part SR1 of the channel layer 140/140e, [0044], Fig. 4) including polycrystalline silicon (second part SR1 of the channel layer 140/140e is converted into polycrystalline silicon using the conductive material (i.e. conductive material for metal induced lateral crystallization (MILC)), [0045], Fig. 4), wherein the first part SR2 is adjacent to the second part SR1 (first part SR2 is adjacent to the second part SR1, [0101], Fig. 13A and 13B).
Claim 14, Kang discloses the memory device (memory device 100, [0028] and [0088], Figs. 10-17) of claim 13.
Kang discloses further comprising a memory layer (gate dielectric layer 150 includes blocking layer 152, charge storage layer 154, and tunneling layer 156 and is a memory layer, hereinafter, memory layer 150, [0050], Fig. 12B) formed in the opening CHH/CHe extending through the stack structure 118/120 and extending along an outer surface of the channel layer 140/140e (memory layer 150 is formed in the opening CHH/CHe extending through the stack structure 118/120 and extending along an outer surface of the channel layer 140/140e, [0050], Fig. 12B).
Claim 15, Kang discloses the memory device (memory device 100, [0028] and [0088], Figs. 10-17) of claim 14.
Kang discloses wherein the memory layer 150 comprises:
a blocking layer 152 contacting an inner surface of the stack structure 118/120 (blocking layer 152 contacting an inner surface of the stack structure 118/120, [0050], Figs. 6B and 12B);
a charge trap layer (charge storage layer 154 is a charge trap layer, hereinafter, charge trap layer 154, [0050], Figs. 6B and 12B) contacting an inner surface of the blocking layer 152 (charge trap layer 154 contacts an inner surface of the blocking layer 152, [0050], Figs. 6B and 12B); and
a tunnel isolation layer (tunneling layer 156 is a tunnel isolation layer, hereinafter, tunnel isolation layer 156, [0050], Figs. 6B and 12B) contacting an inner surface of the charge trap layer 154 and the outer surface of the channel layer 140/140e (tunnel isolation layer 156 contacts an inner surface of the charge trap layer 154 and the outer surface of the channel layer 140/140e, [0050], Figs. 6B and 12B).
Claim 16, Kang discloses the memory device (memory device 100, [0028] and [0088], Figs. 10-17) of claim 13.
Kang discloses further comprising a core pillar (channel buried insulating layer 155 is a core pillar, hereinafter, core pillar 155, [0067], Figs. 6B and 12B) inside the channel layer 140/140e (core pillar 155 is inside the channel layer 140/140e, [0067], Figs. 6B and 12B).
Claim 17, Kang discloses a method (semiconductor device 100 is a memory device, hereinafter, memory device 100, [0028] and [0088], Figs. 10-17) comprising:
forming an opening (channel holes CHH/CHe is an opening, hereinafter, opening CHH/CHe, [0101], Figs. 12A and 12B) extending through a stack structure (opening CHH/CHe extends through the first horizontal sacrificial layers 111, second horizontal sacrificial layers 112, second horizontal conductive layer 104, sacrificial insulating layers 118 and interlayer insulating layers 120 which are a stack structure, hereinafter, stack structure 118/120, [0089], Fig. 10);
forming a channel layer (channel layer 140/140e is formed, [0099], Figs. 12A and 12B) including amorphous silicon in the opening CHH/CHe (channel layer 140/140e includes amorphous silicon in the opening CHH/CHe, [0101], Figs. 12A and 12B);
converting a first part of the channel layer (upper region SR2 of the channel layer 140/140e is a first part of the channel layer, hereinafter, first part SR2 of the channel layer 140/140e, [0044], Fig. 4) into single crystalline silicon (first part SR2 of the channel layer 140/140e is converted to single crystalline silicon, [0101], Fig. 13A and 13B);
doping the first part SR2 of the channel layer 140/140e and a second part SR1 of the channel layer 140/140e with a conductive material (first part SR2 of the channel layer 140/140e and second part SR1 of the channel layer 140/140e may be doped, [0101], Figs. 12A and 12B), wherein the second part SR1 is adjacent to the first part SR2 (second part SR1 is adjacent to the first part SR2, [0045], Figs. 6B and 12B); and
converting the second part SR1 of the channel layer 140/140e into polycrystalline silicon using the conductive material (second part SR1 of the channel layer 140/140e is converted into polycrystalline silicon using the conductive material (i.e. conductive material for metal induced lateral crystallization (MILC)), [0045], Fig. 4).
Claim 18, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 17.
Kang discloses further comprising three separate heat treatments (a plurality of heat treatments may be used including the following; (i) first part SR2 of the channel layer 140/140e is converted into single crystalline silicon by converting the conductive layer 160 into a silicide layer 160 using a first heat treatment (i.e. conductive material for metal induced lateral crystallization (MILC)), [0045], Fig. 4; (ii) crystallization of the first part SR2 is induced by using the silicide layer 160 during a second heat treatment, [0046], Figs. 6B and 12B; and (iii) converting the second part SR1 comprises using a third heat treatment (i.e. recrystallization by high temperature), [0045], Figs. 6B and 12B).
Claim 19, Kang discloses the method (memory device 100, [0028] and [0088], Figs. 10-17) of claim 17.
Kang discloses further comprising:
forming a conductive layer (metal silicide layer 160 is a conductive layer, hereinafter, conductive layer 160, [0067], Figs. 6B and 12B) on the exposed inner surface of the channel layer 140/140e (conductive layer 160 is formed on the exposed inner surface of the channel layer 140/140e, [0067], Figs. 6B and 12B);
converting the conductive layer 160 into a silicide layer using a first heat treatment (first part SR2 of the channel layer 140/140e is converted into single crystalline silicon by converting the conductive layer 160 into a silicide layer 160 using a first heat treatment (i.e. conductive material for metal induced lateral crystallization (MILC)), [0045], Fig. 4); and
inducing crystallization of the first part SR2 by using the silicide layer 160 during a second heat treatment (crystallization of the first part SR2 is induced by using the silicide layer 160 during a second heat treatment, [0046], Figs. 6B and 12B); and
converting the second part SR1 into polycrystalline silicon comprises using a third heat treatment (converting the second part SR1 comprises using a third heat treatment (i.e. recrystallization by high temperature), [0045], Figs. 6B and 12B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Obu (US 2021/0265379 A1) discloses a memory device, comprising: a stack structure 132/142; and a channel layer 60 formed in an opening 49 extending through the stack structure 132/142, wherein the channel layer 60 includes a first part and a second part including polycrystalline silicon, wherein the first part is adjacent to the second part.
Choi (US 2023/0284449 A1) discloses a memory device 100, comprising: a stack structure GS; and a channel layer 140 formed in an opening CH extending through the stack structure GS, wherein the channel layer 140 includes a first part CH2 including single crystalline silicon and a second part CH1 including polycrystalline silicon, wherein the first part CH2 is adjacent to the second part CH1.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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