DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on September 9, 2024 and January 3, 2025 were considered by the Examiner.
Election/Restrictions
Applicant's election with traverse of Invention I, Species A, and Sub-species a1 in the reply filed on July 29, 2026, with claims 1-6, 8, 11-12, 14-16, and 19-20 readable thereon is acknowledged.
Regarding the election of Invention I with traverse, Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement. Accordingly, the election of Invention I has been treated as an election without traverse (MPEP § 818.01(a)).
Regarding the election of Species A with traverse, Applicant argues that claims 1 and 19 recite features common to the disclosed species. While claims 1 and 19 may be generic to the disclosed species, Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement. Accordingly, the election of Species A has been treated as an election without traverse (MPEP § 818.01(a)). Further, even though claims 1 and 19 recite features common to the disclosed species, the species include mutually exclusive characteristics as outlined in the Restriction Requirement mailed on June 23, 2026, such as the different configurations of the p-type and n-type regions relative to the gate 11. Accordingly, there is a serious search and examination burden for the patentably distinct species.
Regarding the election of Sub-species a1 with traverse, Applicant argues that elected and non-elected species share the same generic gate/contact-hole relationship recited in claims 1 and 19. While claims 1 and 19 may be generic to the disclosed sub-species, Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement. Accordingly, the election of Sub-species a1 has been treated as an election without traverse (MPEP § 818.01(a)). Further, even though claims 1 and 19 recite features common to the disclosed sub-species, the sub-species include mutually exclusive characteristics such as different gate and contact hole configurations as outlined in the Restriction Requirement mailed on June 23, 2026. Accordingly, there is a serious search and examination burden for the patentably distinct sub-species.
As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 includes “wherein a shape of the orthographic projection of the first P-type semiconductor region on the semiconductor substrate is similar to a shape of the orthographic projection of the trench structure on the semiconductor substrate” and “similar to a shape” renders this limitation indefinite as this can mean that the shapes are similar in length, width, thickness, in curvature, or something else. Further, the term “similar” is a relative term which renders the claim indefinite. The term “similar” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of this limitation of the invention. As this limitation is part of an optional limitation in claim 3, this limitation is not reinterpreted for the purposes of examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 8, 12, 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2021034621A (“Iwahashi”; citations below are from the attached machine translation which includes paragraph numbers) in view of US20180182886A1 (“Kobayashi”).
RE: Claim 1, Iwahashi discloses A semiconductor device (10 in FIGs. 1-4), comprising:
an N-type semiconductor substrate (21 in FIGs. 2-3, [0023]);
a layer (20, 23, excluding 21, [0023]) disposed on the semiconductor substrate, wherein the layer comprises a first P-type semiconductor region (23 in FIGs. 2-3);
a trench structure (trenches of 40, 50 in FIGs. 1-3, [0026]) disposed at the layer and in contact with the first P-type semiconductor region in a third direction perpendicular to a plane on which the semiconductor substrate is located (upper surface of 32 defines a plane in FIGs. 2-3; FIGs. 2-3 show the trenches of 40, 50 disposed at the layer 20 and in contact with the first P-type semiconductor region 23 in a third z-direction perpendicular to a plane / upper surface of 32 on which the semiconductor substrate 21 is located), wherein a projection of the first P-type semiconductor region in the third direction covers the trench structure (FIGs. 2-3 show a projection of the first P-type semiconductor region 23 in the third z-direction covers the trench structure of 40, 50), the trench structure comprises a plurality of first trenches (50) and one second trench (40), the plurality of first trenches extend in a first direction (y-direction in FIGs. 1, 3) parallel to the plane on which the semiconductor substrate is located, and are arranged at intervals in a second direction (x-direction in FIGs. 1, 3) parallel to the plane on which the semiconductor substrate is located, the second trench extends in the second direction (FIG. 1 shows the second trench of 40 extends in the second x-direction), the second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other (FIG. 1 shows the second trench of 40 and each of the plurality of first trenches 50 are disposed in a cross manner and communicate with each other), and the first direction, the second direction, and the third direction are set in a cross manner (FIG. 1 shows the first y-direction, the second x-direction, and the third z-direction are set in a cross manner);
a gate (44 and/or 54 in FIGs. 2-3, [0033]) filled and disposed in the trench structure, and spaced apart by a gate dielectric layer (lower portions of 42 and/or 52 disposed below source electrode 34 in FIGs. 2-3; 42 and 52 are gate insulating silicon oxide, [0022]);
an interlayer dielectric layer (upper portions of 42, 52 in source electrode 34 which are on 44, 54, and covering 44, 54 in FIGs. 2-3) disposed on the gate and covering the gate, wherein the interlayer dielectric layer has a contact hole (contact hole in the upper portions of 42 in FIG. 2) that extends in the second direction (the contact hole exposes regions of 26, 27 between 40 in FIG. 1, and extends in the second x-direction), the contact hole exposes a partial region of the layer (FIG. 2 shows the contact hole exposes a partial region 26, 27 of the layer 20), and a projection of the contact hole in the third direction does not overlap the gate (FIG. 2 shows a projection of the contact hole in the third z-direction does not overlap the gate 44, 54);
a source (34, [0029]) disposed at the interlayer dielectric layer, wherein the source is in contact, through the contact hole, with the layer exposed by the contact hole (FIG. 2 shows the source 34 is in contact, through the contact hole, with partial region 26, 27 of the layer 20 exposed by the contact hole), and the source is connected to the first P-type semiconductor region (FIG. 2 shows 34 is connected to 23); and
a drain (32, [0024]) disposed on a side (bottom side of 21) of the semiconductor substrate and away from the layer.
Iwahashi does not explicitly disclose:
the layer is an epitaxial layer.
However, Iwahashi discloses The drain region 21 is also a base substrate for epitaxially growing the drift region 22, [0024].
In the same field of endeavor, Kobayashi discloses in FIG. 1:
the silicon carbide base 10 is formed by sequentially forming plural silicon carbide layers including an n−-type drift layer 2 (2 a, 2 b) and an n+-type source layer 4 by epitaxial growth on an n+-type supporting substrate (n+-type silicon carbide substrate) containing silicon carbide, [0024], see also FIGs. 2-8 showing the semiconductor device during manufacture.
In FIG. 1, the silicon carbide base 10 is shown as including all the semiconductor layers on the semiconductor substrate 1 between the source electrode 11 and the drain electrode 12, [0033].
Kobayashi discloses The semiconductor device and the method of manufacturing a semiconductor device according to the present invention achieve effects in that punch-through may be prevented and the contact resistance may be reduced, [0066].
In Iwahashi FIG. 2, the semiconductor layers 22, 23, 24, 25, 26, 27, 28 are all the semiconductor layers on the semiconductor substrate 21 between the source 34 and drain 32.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the semiconductor layers 22, 23, 24, 25, 26, 27, 28 by epitaxial growth on the substrate 21 as taught by Kobayashi in order to prevent punch-through effects and reduce contact resistance.
RE: Claim 2, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 1, wherein an edge of an orthographic projection of the first P-type semiconductor region on the semiconductor substrate is located beyond an edge of an orthographic projection of the trench structure on the semiconductor substrate (Iwahashi FIG. 2 shows an edge of an orthographic projection of the first P-type semiconductor region 23 on the semiconductor substrate 21 is located beyond an edge of an orthographic projection of the trench structure 40 on the semiconductor substrate 21).
RE: Claim 3, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 1, wherein a shape of the orthographic projection of the first P-type semiconductor region on the semiconductor substrate is similar to a shape of the orthographic projection of the trench structure on the semiconductor substrate (this limitation is considered optional due to the presence of “or”); or
the projection of the first P-type semiconductor region in the third direction covers a gap between adjacent first trenches in the plurality of first trenches (Iwahashi FIG. 3 shows the projection of the first P-type semiconductor region 23 / corner region of 23 in the third z-direction covers a gap between adjacent first trenches 50 in the plurality of first trenches).
RE: Claim 4, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 1, wherein the epitaxial layer further comprises a first N-type semiconductor region (22 in Iwahashi FIG. 2), a second N-type semiconductor region (24 in Iwahashi FIG. 2), a second P-type semiconductor region (25 in Iwahashi FIG. 2), and a source region (27 in Iwahashi FIG. 2, [0023]) that are sequentially disposed on the semiconductor substrate;
the first P-type semiconductor region is disposed in the first N-type semiconductor region (Iwahashi FIG. 2 shows the first P-type semiconductor region 23 is in 22), and in the third direction, the trench structure extends to the first N-type semiconductor region (Iwahashi FIG. 2 shows and in the third z-direction, the trench structure 40 extends to the first N-type semiconductor region 22); and
the contact hole exposes a partial region of the source region (Iwahashi FIG. 2 shows the contact hole in the upper portions of 42 exposes a partial upper region of 27).
RE: Claim 5, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 4, wherein the epitaxial layer further comprises:
a third P-type semiconductor region (In Iwahashi FIG. 3: left 28 on left sidewall of the left trench 50) disposed on at least one side wall of the trench structure, and in contact with the first P-type semiconductor region (FIG. 3 shows left 28 in contact with the first P-type semiconductor region 23); and
a fourth P-type semiconductor region (In Iwahashi FIG. 3: right 28 on right sidewall of the left trench 50), wherein the fourth P-type semiconductor region and the source region are disposed at a same layer (Iwahashi FIG. 3 shows 28 and source region 27 are disposed at a same layer or interface), and the fourth P-type semiconductor region and the third P-type semiconductor region are disposed in a one-to-one correspondence and are in contact with each other (Iwahashi FIG. 3 shows the left 28 and right 28 on sidewalls of the left trench are disposed in a one-to-one correspondence, and are in indirect contact with each other through 50 or 23, or are in electrical contact with each other through 23).
RE: Claim 6, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 5, wherein each of the plurality of first trenches has a first side wall and a second side wall that are disposed opposite to each other in the first direction (Iwahashi FIG. 3 shows each of the plurality of first trenches 50 has a first left side wall and a second right side wall that are disposed opposite to each other in the first y-direction); and
the third P-type semiconductor region is disposed on a first side wall and/or a second side wall of at least one of the plurality of first trenches (Iwahashi FIG. 3 shows the left 28 is disposed on a first left side wall of the left trench of 50), or the fourth P-type semiconductor region is in contact with the source through the contact hole.
RE: Claim 8, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 6, wherein a width of the fourth P- type semiconductor region is equal to a width of the first trench (Iwahashi FIG. 1 shows a horizonal width of the fourth P- type semiconductor region 28 is equal to a width of the first trench 50), and a trench spacing between two adjacent first trenches is equal to a width of the source region (Iwahashi FIG. 1 shows a trench spacing between two adjacent first trenches 50 is equal to a horizontal width of the source n+ region 27).
RE: Claim 12, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 5, wherein in the third direction, the first P-type semiconductor region covers the third P-type semiconductor region (Iwahashi FIG. 3 shows wherein in the third z-direction, the first P-type semiconductor region 23 covers the third P-type semiconductor region 28).
RE: Claim 15, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 4, wherein a doping concentration of the semiconductor substrate is greater than a doping concentration of the second N-type semiconductor region (Kobayashi discloses Additionally, + or − appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or −, [0022]; Kobayashi FIG. 1 shows substrate 1 is n+ and 2b is n; Accordingly, Kobayashi discloses a doping concentration of a semiconductor substrate 1 is greater than a doping concentration of a second N-type semiconductor region 2b), and the doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region (Kobayashi FIG. 1 shows 2a is n-; Accordingly, Kobayashi discloses the doping concentration of the second N-type semiconductor region 2b is greater than the doping concentration of a first N-type semiconductor region 2a).
RE: Claim 16, Iwahashi in view of Kobayashi discloses The semiconductor device according to claim 1, wherein materials of the semiconductor substrate and the epitaxial layer are SiC (Iwahashi discloses the semiconductor substrate 20 is a substrate made of silicon carbide (SiC), [0023]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable Iwahashi in view of Kobayashi as applied to claim 5 above, further in view of US20210408278A1 (“Okumura”).
RE: Claim 11, Iwahashi in view of Kobayashi does not disclose The semiconductor device according to claim 5, wherein doping concentrations of the first P-type semiconductor region, the third P-type semiconductor region, and the fourth P- type semiconductor region are greater than a doping concentration of the second P-type semiconductor region.
In the same field of endeavor, Okumura discloses in FIG. 6:
wherein doping concentrations of a first P-type semiconductor region (3b is p+), a third P-type semiconductor region (left region 4b is p+; the second p+-type base regions 4 b may be provided at both sidewalls, [0063]), and a fourth P- type semiconductor region (right region 4b is p+) are greater than a doping concentration of a second P-type semiconductor region (6 is p in FIGs. 1A and 6; Additionally, + or − appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or −, [0032]).
Okumura further discloses As a result, punch-through may be prevented and the withstand voltage may be sustained to a greater extent, [0063].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form doping concentrations of the first P-type semiconductor region, the third P-type semiconductor region, and the fourth P- type semiconductor region to be greater than a doping concentration of the second P-type semiconductor region as taught by Okumura in order to prevent punch-through and sustain withstand voltage to a greater extent.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable Iwahashi in view of Kobayashi as applied to claim 4 above, further in view of US20240038851A1 (“Tawara”), further in view of US20180182887A1 (“Tawara-2”).
RE: Claim 14, Iwahashi in view of Kobayashi does not explicitly disclose The semiconductor device according to claim 4, wherein the epitaxial layer further comprises a third N-type semiconductor region disposed between the first N-type semiconductor region and the semiconductor substrate, and a doping concentration of the third N-type semiconductor region is less than a doping concentration of the first N-type semiconductor region; and
a thickness of the first P-type semiconductor region is greater than 1 µm.
In the same field of endeavor Tawara discloses in FIG. 1:
a third N-type semiconductor region (epitaxial layer 2 is n-, [0035]) disposed between a first N-type semiconductor region (6a is n, [0036]) and a semiconductor substrate (1 is n+), and a doping concentration of a third N-type semiconductor region is less than a doping concentration of the first N-type semiconductor region (Additionally, + or − appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without+ or −, [0033]; Accordingly, Tawara discloses a doping concentration of a third N-type semiconductor region 2 is less than a doping concentration of the first N-type semiconductor region 6a).
Tawara further discloses the short-circuit current is lowered while the device on-resistance is maintained as is, thereby, enabling improvement of the short-circuit capability, [0081].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a third N-type semiconductor region disposed between the first N-type semiconductor region and the semiconductor substrate as taught by Tawara in order to lower short-circuit current.
In the same field of endeavor, Tawara-2 discloses a first p-type embedded layer 3 a that has, for example, a width of 2 μm, [0059].
Tawara-2 further discloses increases in the resistance of the drift layer and the source layer may be prevented, [0075].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first P-type semiconductor region with a width/thickness of 2 μm as taught by Tawara-2 in order to prevent resistance of the source layer.
Claims 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwahashi in view of Kobayashi, further in view of US20120025298 A1 (“Ho”).
RE: Claim 19, Iwahashi discloses A power conversion circuit (10 in FIGs. 1-4) comprising:
one or more semiconductor devices (10 in FIGs. 1-4), the one or more semiconductor devices comprising:
an N-type semiconductor substrate (21 in FIGs. 2-3, [0023]);
a layer (20, 23, excluding 21, [0023]) disposed on the semiconductor substrate, wherein the layer comprises a first P-type semiconductor region (23 in FIGs. 2-3);
a trench structure (trenches of 40, 50 in FIGs. 1-3, [0026]) disposed at the layer and in contact with the first P-type semiconductor region in a third direction perpendicular to a plane on which the semiconductor substrate is located (upper surface of 32 defines a plane in FIGs. 2-3; FIGs. 2-3 show the trenches of 40, 50 disposed at the layer 20 and in contact with the first P-type semiconductor region 23 in a third z-direction perpendicular to a plane / upper surface of 32 on which the semiconductor substrate 21 is located), wherein a projection of the first P-type semiconductor region in the third direction covers the trench structure (FIGs. 2-3 show a projection of the first P-type semiconductor region 23 in the third z-direction covers the trench structure of 40, 50), the trench structure comprises a plurality of first trenches (50) and one second trench (40), the plurality of first trenches extend in a first direction (y-direction in FIGs. 1, 3) parallel to the plane on which the semiconductor substrate is located, and are arranged at intervals in a second direction (x-direction in FIGs. 1, 3) parallel to the plane on which the semiconductor substrate is located, the second trench extends in the second direction (FIG. 1 shows the second trench of 40 extends in the second x-direction), the second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other (FIG. 1 shows the second trench of 40 and each of the plurality of first trenches 50 are disposed in a cross manner and communicate with each other), and the first direction, the second direction, and the third direction are set in a cross manner (FIG. 1 shows the first y-direction, the second x-direction, and the third z-direction are set in a cross manner);
a gate (44 and/or 54 in FIGs. 2-3, [0033]) filled and disposed in the trench structure, and spaced apart by a gate dielectric layer (lower portions of 42 and/or 52 disposed below source electrode 34 in FIGs. 2-3; 42 and 52 are gate insulating silicon oxide, [0022]);
an interlayer dielectric layer (upper portions of 42, 52 in source electrode 34 which are on 44, 54, and covering 44, 54 in FIGs. 2-3) disposed on the gate and covering the gate, wherein the interlayer dielectric layer has a contact hole (contact hole in the upper portions of 42 in FIG. 2) that extends in the second direction (the contact hole exposes regions of 26, 27 between 40 in FIG. 1, and extends in the second x-direction), the contact hole exposes a partial region of the layer (FIG. 2 shows the contact hole exposes a partial region 26, 27 of the layer 20), and a projection of the contact hole in the third direction does not overlap the gate (FIG. 2 shows a projection of the contact hole in the third z-direction does not overlap the gate 44, 54);
a source (34, [0029]) disposed at the interlayer dielectric layer, wherein the source is in contact, through the contact hole, with the layer exposed by the contact hole (FIG. 2 shows the source 34 is in contact, through the contact hole, with partial region 26, 27 of the layer 20 exposed by the contact hole), and the source is connected to the first P-type semiconductor region (FIG. 2 shows 34 is connected to 23); and
a drain (32, [0024]) disposed on a side (bottom side of 21) of the semiconductor substrate and away from the layer.
Iwahashi does not explicitly disclose:
the layer is an epitaxial layer;
a circuit board; and
the one or more semiconductor devices are connected to the circuit board.
However, Iwahashi discloses The drain region 21 is also a base substrate for epitaxially growing the drift region 22, [0024].
In the same field of endeavor, Kobayashi discloses in FIG. 1:
the silicon carbide base 10 is formed by sequentially forming plural silicon carbide layers including an n−-type drift layer 2 (2 a, 2 b) and an n+-type source layer 4 by epitaxial growth on an n+-type supporting substrate (n+-type silicon carbide substrate) containing silicon carbide, [0024], see also FIGs. 2-8 showing the semiconductor device during manufacture.
In FIG. 1, the silicon carbide base 10 is shown as including all the semiconductor layers on the semiconductor substrate 1 between the source electrode 11 and the drain electrode 12, [0033].
Kobayashi discloses The semiconductor device and the method of manufacturing a semiconductor device according to the present invention achieve effects in that punch-through may be prevented and the contact resistance may be reduced, [0066].
In Iwahashi FIG. 2, the semiconductor layers 22, 23, 24, 25, 26, 27, 28 are all the semiconductor layers on the semiconductor substrate 21 between the source 34 and drain 32.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the semiconductor layers 22, 23, 24, 25, 26, 27, 28 by epitaxial growth on the substrate 21 as taught by Kobayashi in order to prevent punch-through effects and reduce contact resistance.
Further, Iwahashi discloses The semiconductor device 10 of the present embodiment shown in FIGS. 1 to 3 is a power semiconductor element called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), [0020].
In the same field of endeavor, Ho discloses:
Embodiments of the present invention are particularly advantageous in power MOSFET applications. For example, conventional DC-DC power converters using MOSFET power devices often require a high-side NMOSFET and a low-side NMOSFET. Conventional vertical MOSFET devices are bottom drain. In power converter package, the high-side source and the low-side drain are typically connected to each other with additional bond wires and the low-side source may be electrically coupled to a lead frame. Embodiments of the present invention with the gate, source and drain electrodes on both sides of the device, and which can be contacted from the side of the device, allow stacked co-packaging of high-side (HS) and low-side (LS) MOSFETs to form a DC-DC power converter half bridge, or stacking multiple MOSFET dies connected in parallel to improve the on-resistance (R.sub.on), as well as stacking a capacitor on the DC-DC power converter to enhance performance in model and board level, [0039].
Ho further discloses The cross-sectional diagram of FIG. 8B illustrate an advantage of stacked co-packaging assembly of a high-side NMOSFET HS and a low-side NMOSFET LS that include gate, source and drain electrode contacts on both sides of the device. As shown in FIG. 8B, the high-side NMOSFET HS can be stacked on top of the low-side NMOSFET LS. The source of the high-side NMOSFET can be electrically connected to the drain of the low-side NMOSFET with a solder paste SP using the wraparound sidewall contacts as described herein. The low side MOSFET may be mounted onto a printed circuit board (PCB) (not shown) with solder paste SP. Stacking MOSFETs allows for more efficient use of space on the circuit board, [0042].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to stack multiple MOSFETs 10 on a circuit board in order to enhance performance in model and board level as further taught by Ho, [0039].
RE: Claim 20, Iwahashi in view of Kobayashi, Ho discloses The power conversion circuit of claim 19, wherein the power conversion circuit is configured to convert an alternating current and/or a direct current and output a direct current (Ho discloses conventional DC-DC power converters use MOSFET power devices, [0039]; Accordingly, Ho discloses the power conversion circuit is configured to convert a direct current (DC) and output a direct current (DC);
Alternatively:
The limitation “the power conversion circuit is configured to convert an alternating current and/or a direct current and output a direct current” is an intended use limitation.
MPEP 2114 states "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim;
As the modified power conversion circuit teaches all the structural limitations of the claim, it meets the claim limitations).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
