Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 5/6/2024.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Priority
Applicant' s claim for the benefit of prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to China application serial no. 202310649663.5, filed on June 2, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/6/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: PIXEL ELECTRODE WITH FIRST AND SECOND CONDUCTIVE MATERIAL OF DIFFERING THICKNESSES AND MANUFACTURING METHOD THEREOF
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show "a thickness of the first conductive layer is. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show "a top surface of the second conductive layer is . Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 7 is objected to because of the following informalities: in the middle of the list of materials the phrase “an alloy thereof or a compound thereof” and is then immediately followed by a second list of materials which is ended with “a combination thereof”. This may lead to confusion on as to the intended combination of material and if it necessarily should include at least one of the materials of the first set and at least one of the materials from the second set of materials. Or if the material is supposed to be treated as a single set of material to choose from.
Examiner suggests the following amendment:
7. The electronic device of claim 1, wherein a material of the first conductive layer comprises gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), .
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 20120268396 A1.
The following drawing will be used in discussion:
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Regarding claim 1, Kim discloses:
An electronic device, (Fig. 3, liquid crystal display (LCD) device) comprising:
a substrate; (substrate 101) and
a plurality of control units (annotated Fig. 3, control unit) disposed on the substrate, wherein one of the plurality of control units comprises:
a transistor (thin film transistor Tr) comprising a first electrode (second semiconductor region 113b);
an insulating layer (interlayer insulating layer 123) disposed on the transistor (Tr) and having a through hole (including semiconductor contact hole 125 and second drain contact hole 157) exposing the first electrode; (second semiconductor region 113b)
a first conductive layer (including source and drain electrodes 136 and an etching preventing pattern 151) disposed on the transistor (transistor Tr), wherein a portion of the first conductive layer is overlapped with the insulating layer, (See Fig. 3) and another portion of the first conductive layer is electrically connected to the first electrode via the through hole; and (See Fig. 3)
a second conductive layer (pixel electrode 160) at least partially overlapped with the first conductive layer (including source and drain electrodes 136 and an etching preventing pattern 151) and in direct contact with the first conductive layer (See Fig.3), wherein in a top view, an area of the second conductive layer is greater than an area of the first conductive layer. (See related Fig. 1 for the top view where transistor TR is located, the pixel electrode 160 in the drawing Fig. 3 is over a greater area than the first conductive layer.)
Regarding claim 5, Kim further discloses:
the second conductive layer comprises a transparent conductive material. ([0050], A pixel electrode 160 of a transparent conductive material such as indium-tin-oxide (ITO).)
Regarding claim 6, Kim further discloses:
a material of the first conductive layer is different from a material of the second conductive layer. ([0037]-[0038], The material of the drain electrode 136 is the same material as the data line 130 which includes aluminum.)
Regarding claim 7, Kim further discloses:
a material of the first conductive layer comprises gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), an alloy thereof or a compound thereof, indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), antimony tin oxide (ATO), fluorine-doped tin oxide (FTO), or a combination thereof. ( ([0037]-[0038], The material of the drain electrode 136 is the same material as the data line 130 which includes aluminum. [0042] –[0043], the material of the etching preventing pattern 151 may be material as the common electrode which includes indium-zinc-oxide (IZO).)
Regarding claim 8, Kim further discloses:
a material of the second conductive layer comprises indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), antimony tin oxide (ATO), fluorine-doped tin oxide (FTO), or a combination thereof. ([0050], A pixel electrode 160 of a transparent conductive material such as indium-tin-oxide (ITO).)
Regarding claim 9, Kim further discloses,
a portion of the second conductive layer is disposed in the through hole of the insulating layer. (See Fig.3, pixel electrode 160 has a portion of it that is disposed in the drain contact hole 157.)
Regarding claim 10, Kim further discloses:
adjacent to the through hole, ( (including semiconductor contact hole 125 and second drain contact hole 157) a top surface of the second conductive layer (pixel electrode 160) is higher than a top surface of the first conductive layer, (Fig. 3, the top layer of of the pixel electrode 160 is higher than etching preventing pattern 151.) and the top surface of the first conductive layer is higher than a top surface of the insulating layer. (Fig. 3, the top surface of the etching preventing pattern 151 is higher than interlayer insulating layer 123.)
Regarding claim 11, Kim further discloses:
a plurality of first wires (Fig. 1, shows in the top view that there is a plurality of gate lines 14,) and a plurality of second wires (a plurality of data lines 16) are disposed on the substrate (substrate 12), the plurality of first wires are respectively extended along a first direction, (See Fig. 1, the gate lines 14 are in a first direction.) and the plurality of second wires are respectively extended along a second direction, (Data lines 16 are extended long a second direction.) wherein the first direction is different from the second direction, (Fig. 1, the first direction is perpendicular from each other.) and the one of the plurality of control units is located in a region surrounded by two adjacent first wires and two adjacent second wires. ( the control unit is in the area of the transistor Tr.)
Regarding claim 12, Kim further discloses:
a plurality of opening regions, and in the top view, one of the plurality of opening regions is located in the region surrounded by the two adjacent first wires and the two adjacent second wires. (See Fig.1 in conjunction with Fig. 3 , in the top view shows the area of the location of the transistor Tr which would have and adjacent wiring area that shows the opening area in the pixel electrode area 18. See also annotated Fig. 3 for the opening area.)
Regarding claim 13, Kim further discloses:
in the top view, each of the plurality of opening regions exposes a portion of the second conductive layer. (See annotated Fig. 3, pixel electrode 160 is in the opening region.)
Regarding claim 14, Kim further discloses:
the first conductive layer is located outside each of the plurality of opening regions. (See annotated Fig. 3, drain electrodes 136 and an etching preventing pattern 151 is outside the opening region.)
Regarding claim 15, Kim discloses:
A manufacturing method of an electronic device, (Fig. 3 and methods steps shown in 6A-6J) , liquid crystal display (LCD) device) comprising:
forming a transistor (Fig. 6E, transistor Tr) on a substrate; (Fig. 6D, forming substrate 101)
forming a planar layer on the transistor, (Fig. 6D, interlayer insulating layer 123) wherein the planar layer has a first through hole (Fig. 6D, semiconductor contact hole 125) exposing a portion of the transistor; (second semiconductor region 113b exposed before the deposition of the drain electrodes 136)
forming an insulating layer (Fig. 6G, first passivation layer 145) on the planar layer, (interlayer insulating layer 123) wherein the insulating layer has a second through hole, and the second through hole (first drain contact hole 147) of the insulating layer is overlapped with the first through hole (semiconductor contact hole 125) of the planar layer in a normal direction of the substrate; (See Fig. 6G, the through hole goes in the direction of the substrate 101)
forming a first conductive layer (Fig. 6G, etching preventing pattern 151) on the insulating layer, (first passivation layer 145) wherein a portion of the first conductive layer is overlapped with the insulating layer, (See Fig. 6G.) and another portion of the first conductive layer (etching preventing pattern 151) is electrically connected to the transistor (transistor Tr) via the second through hole (first drain contact hole 147) of the insulating layer; (first passivation layer 145) and
forming a second conductive layer (Fig. 6J, pixel electrode 160) on the insulating layer, (first passivation layer 145) wherein the second conductive layer (pixel electrode 160) is at least partially overlapped with the first conductive layer (etching preventing pattern 151), and the second conductive layer is in direct contact with the first conductive layer. (See Fig. 6J, there is a portion of the pixel electrode 160 is in direct contact with the etching preventing pattern 151.)
Regarding claim 16, Kim further discloses:
in the step of forming the second conductive layer on the insulating layer, a portion of the second conductive layer is formed in the second through hole of the insulating layer. (See Fig. 6J, there is a portion of pixel electrode 160 is inside the first drain contact hole 147.)
Regarding claim 17, Kim further discloses:
forming a plurality of first wires on the substrate; and (Fig. 1, shows in the top view that there is a plurality of gate lines 14 is on the substrate 12.)
forming a plurality of second wires on the substrate, (a plurality of data lines 16)
wherein the plurality of first wires are respectively extended along a first direction, (See Fig. 1, the gate lines 14 are in a first direction.) the plurality of second wires are respectively extended along a second direction, (Data lines 16 are extended long a second direction.) the first direction is different from the second direction, Fig. 1, the first direction is perpendicular from each other.) and the transistor is located in a region surrounded by two adjacent first wires and two adjacent second wires. (The control unit is in the area of the transistor Tr which is adjacent to the area of the gate lines 14 and data lines 16.)
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claim 3, Kim discloses a first conductive layer (including source and drain electrodes 136 and an etching preventing pattern 151) which would by necessity have some thickness. The electronic device of claim 1, wherein a thickness of the first conductive layer is between 50 nm to 70 nm. Although Kim does not teach that the "thickness of the first conductive layer is between 50 nm to 70 nm", where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions does not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)). In this case, nothing on the record indicates that the claimed thickness of first conductive layer would cause the structure to operate differently.
Regarding claim 4, Kim discloses the second conductive layer (pixel electrode 160) which would by necessity have some thickness. Although Kim does not teach that the "thickness of the second conductive layer is between 5 nm to 50 nm", where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions does not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)). In this case, nothing on the record indicates that the claimed thickness of second conductive layer would cause the structure to operate differently.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 15 above, and further in view of Yamaguchi, US 11488984 B2 (hereinafter Yamaguchi).
Regarding claim 18, Kim discloses all the elements of claim 15.
Kim further discloses:
forming a semiconductor layer on the substrate; (Fig. 6B, a semiconductor layer 113)
forming a gate insulating layer, (gate insulating layer 116) a first metal layer, (gate electrode 120) and …. on the substrate (substrate 101); and
forming a second metal layer (a source electrode 133 and drain electrodes 136) on the interlayer insulating layer. (interlayer insulating layer 123)
Kim does disclose a the planar layer, (interlayer insulating layer 123) that is over the transistor. Kim does not appear to specifically disclose that there is an “ interlayer insulating layer” on the substrate.
However, Yamaguchi, which teaches a transistor is used in a pixel circuit (Yamaguchi, Background, Col. 1, lines 25-26.), discloses:
forming a gate insulating layer (Fig. 17, insulating layer 344B), a first metal layer, (gate electrode 930B) and an interlayer insulating layer (insulating layer 348B) on the substrate (substrate 301B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim to have interlayer insulating layer over the transistor as taught by Yamaguchi for purposes of providing electrical insulation over the transistor.
Regarding claim 19, Kim and Yamaguchi discloses all the element of claim 18.
Kim further discloses:
the first metal layer comprises a gate(Fig. 6B, gate electrode), and the second metal layer comprises a source and a drain (a source electrode 133 and drain electrodes 136).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 15 above, and further in view of Liu et al. US 20240088300 A1 (hereinafter Liu).
Regarding claim 20, Kim discloses all the elements of claim 15.
Kim further discloses:
forming a buffer layer(Fig. 6A, buffer layer 105) on the substrate (substrate 101).
Kim does not appear to disclose:
forming a light-shielding layer on the substrate; and
…., wherein the buffer layer covers the light-shielding layer.
Lui, which disclose an OLED (Lui, Background [0002] which includes thin film transistor with a light shielding layer (Abstract), discloses:
forming a light-shielding layer (Liu, Fig. 3, first light shielding layer LS1) on the substrate (substrate 11) ; and
forming a buffer layer (buffer layer 16) on the substrate (substrate 11), wherein the buffer layer covers the light-shielding layer. (See Fig. 3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim to have forming a light-shielding layer on the substrate, and the buffer layer covers the light-shielding layer as taught by Lui for purposes of being used to shield the active layer above it from light and preventing the light from affecting the stability of the active layer. (Liu, [0107].)
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, an electronic device comprising “a thickness of the first conductive layer is less than a thickness of the second conductive layer”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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