Prosecution Insights
Last updated: October 04, 2026
Application No. 18/656,568

ELECTRONIC DEVICE

Non-Final OA §102§103§112
Filed
May 06, 2024
Examiner
DAS, PINAKI
Art Unit
Tech Center
Assignee
Advanced Semiconductor Engineering Korea Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
46 granted / 53 resolved
+26.8% vs TC avg
Minimal -2% lift
Without
With
+-1.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
33 currently pending
Career history
90
Total Applications
across all art units

Statute-Specific Performance

§103
51.2%
+11.2% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
22.3%
-17.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 53 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species II in the reply filed on 8/3/2026 is acknowledged. Information Disclosure Statement Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 16 recites the limitation wherein “a plurality of vias within the encapsulant and configured to define a capacitor component.” It is unclear how the vias will be configured to define a capacitor component, particularly what configurations would be necessary and how that would be implemented. Hence, the claim is indefinite and therefore rejected. Claims 17-20 depend from claim 16 and inherit the same indefiniteness. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 5-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kao et al. (US 2020/0411636 A1). Re Claim 1, Kao teaches an electronic device (Fig. 1), comprising: a first electronic component (110, Fig. 1, para [0014]); an encapsulant (102, Fig. 1, para [0014]) encapsulating the first electronic component (110); a first capacitor (103, Fig. 1, para [0019]) having a first depth (103 having a 1st depth, see Fig. 1) extending from an upper surface of the encapsulant (upper surface of 102); and a second capacitor (101, Fig. 1, para [0019]) having a second depth (101 having a 2nd depth, see Fig. 1), different from the first depth (2nd depth is larger than 1st depth, see Fig. 1), extending from the upper surface of the encapsulant (upper surface of 102). Re Claim 2, Kao teaches the electronic device of claim 1, wherein the first electronic component (110) vertically overlaps (see Fig. 1) the first capacitor (103). Re Claim 5, Kao teaches the electronic device of claim 1, wherein a first electrode (118, Fig. 1, para [0019]) of the first capacitor (103, Fig. 1) is exposed by the upper surface of the encapsulant (upper surface of 102), and a second electrode (114, Fig. 1, para [0019]) of the first capacitor (103) vertically overlaps (see Fig. 1) the first electrode (118). Re Claim 6, Kao teaches the electronic device of claim 1, wherein the encapsulant (102, Fig. 1) defines a trench (marked “trench” in annotated Fig. 1 below) accommodating a first electrode (118, Fig. 1, para [0019]) and a second electrode (114, Fig. 1, para [0019]) of the first capacitor (103). PNG media_image1.png 421 625 media_image1.png Greyscale Re Claim 7, Kao teaches the electronic device of claim 6, wherein the first electrode (118, Fig. 1) of the first capacitor (103) extends from the upper surface of the encapsulant (upper surface of 102) to a bottom of the trench (see Fig. 1). Re Claim 8, Kao teaches the electronic device of claim 6, wherein the first electrode (118, Fig. 1) comprises a first portion over the upper surface of the encapsulant (portion of 118 that is above the top surface of 102, see Fig. 1), and the second electrode (114, Fig. 1) comprises a second portion over the upper surface of the encapsulant (portion of 114 that is above the top surface of 102, see Fig. 1). Re Claim 9, Kao teaches the electronic device of claim 7, wherein the first electrode (118, Fig. 1) further comprises a third portion (portion of 118 that is vertically extending within the trench, see Fig. 1) extending along a lateral surface (vertical side surface of 102 that defines the trench, see annotated Fig. 1 above) connected to the upper surface of the encapsulant (upper surface of 102). Re Claim 10, Kao teaches the electronic device of claim 8, further comprising: a carrier (104, Fig. 1, paras [0015] – [0016]) supporting the first electronic component (110); and a conductive wire (110a, Fig. 1, para [0017]) electrically connecting the first electronic component (110) and the carrier (104). Re Claim 11, Kao teaches an electronic device, comprising: an electronic component (110, Fig. 1, para [0014]); an encapsulant (102, Fig. 1, para [0014]) encapsulating the electronic component (110); and a first capacitor (103, Fig. 1, para [0019]) accommodated by the encapsulant (102), wherein the first capacitor (103) extends along a first direction (vertical direction in Fig. 1) substantially orthogonal to an upper surface (upper surface of 102), spaced apart from the electronic component (110), of the encapsulant (102), and the first capacitor (103) overlaps (see Fig. 1) the electronic component (110) along the first direction (vertical direction in Fig. 1). Re Claim 12, Kao teaches the electronic device of claim 11, wherein the encapsulant (102) defines a trench (marked “trench” in annotated Fig. 1 above) extends along the first direction (vertical direction in Fig. 1) and accommodating the first capacitor (103). Re Claim 13, Kao teaches The electronic device of claim 12, wherein the first capacitor (103) comprises a deep trench capacitor (see Fig. 1). Re Claim 14, Kao teaches the electronic device of claim 11, further comprising: a carrier (120, Fig. 1, paras [0020] – [0021]) supporting the electronic component (110); a first conductive wire (122a + “124-1”, marked in annotated Fig. 1 below, paras [0022] - [0023]) connecting a first electrode (114, Fig. 1, para [0019]) of the first capacitor (103) and the carrier (120); and a second conductive wire (122b + “124-2”, marked in annotated Fig. 1 below, paras [0022] - [0023]) connecting a second electrode (118, Fig. 1, para [0019]) of the first capacitor (103) and the carrier (120), wherein a top of the first conductive wire (top surface of 122a) is in a level different from a level of a top of the second conductive wire (top surface of 122b, see Fig. 1). PNG media_image2.png 406 685 media_image2.png Greyscale Re Claim 15, Kao teaches the electronic device of claim 14, wherein the top of the second conductive wire (top surface of 122b) is protruded from the upper surface of the encapsulant (upper surface of 102), and a lateral surface of the second conductive wire (horizontal side-surface of 122b) is nonparallel to a lateral surface of the first electrode (vertical-side surface of 114). Claims 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Darmawikarta et al. (US 2022/0392855 A1). Re Claim 16, Darmawikarta teaches an electronic device (Fig. 1A), comprising: an electronic component (114-2, Fig. 1A, para [0024]); an encapsulant (133, Fig. 1A, para [0038], also see Figs. 2A-2C showing how it is formed) encapsulating the electronic component (114-2), wherein the encapsulant comprises a molding material and fillers within the molding material (mold material with inorganic silica particles, para [0038]); and a plurality of vias (vias where capacitors “190A-1” and “190A-2” are formed, annotated in Figs. 1A-1B below, para [0022]) within the encapsulant (133) and configured to define a capacitor component (para [0022]). PNG media_image3.png 509 848 media_image3.png Greyscale Re Claim 17, Darmawikarta teaches the electronic device of claim 16, wherein the plurality of vias comprise a first electrode (198B, Figs. 1A-1B, para [0022]) and a second electrode (192B, Figs. 1A-1B, para [0022]) spaced apart from the first electrode by a dielectric layer (194, Figs. 1A-1B, para [0022]). Re Claim 18, Darmawikarta teaches the electronic device of claim 17, wherein a top of the first electrode (top surface of 198B) is at a level different (see Fig. 1A) from a level of a top of the second electrode (top surface of 192B) with respect to an upper surface of the encapsulant (upper surface of 133, marked in annotated Fig. 1A above). Re Claim 19, Darmawikarta teaches the electronic device of claim 17, wherein the first electrode (198B) and the second electrode (192B) overlap a lateral surface of the encapsulant (marked “lateral side surface of 133” in annotated Fig. 1A above). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 2022/0392855 A1), and further in view of Huang et al. (US 2016/0276248 A1). Re Claim 20, Darmawikarta teaches the electronic device of claim 16, further comprising: a carrier (102, Fig. 1A, para [0021]) supporting the encapsulant (133), wherein a first via (1st via where capacitor “190A-1” is formed, see annotated Fig. 1A below) of the plurality of vias comprises a first electrode (marked “198B-1” in annotated Fig. 1A below) extending from an upper surface of the encapsulant (upper surface of 133, marked in annotated Fig. 1A below) to the carrier (102), a second via (2nd via where capacitor “190A-2” is formed, see annotated Fig. 1A below) of the plurality of vias comprises a second electrode (marked “198B-2” in annotated Fig. 1A below) extending from the upper surface of the encapsulant (upper surface of 133, marked in annotated Fig. 1A below) to the carrier (102), and the first electrode is electrically coupled to the second electrode (“198B-1” and “198B-2” are electrically connected); and a conductive wire (conductive pillar 152, Fig. 1A, para [0024]) electrically connected to the first electrode and the second electrode (152 is electrically connected to “198B-1” and “198B-2”, via the die 114-3, see Fig. 1A). PNG media_image4.png 520 838 media_image4.png Greyscale Darmawikarta does not disclose that the conductive pillar (152, Fig. 1A) has a curved lateral surface. Related art Huang teaches that the conductive metal posts (38, Figs. 21 and 29, para [0017]) can have a straight vertical surface (pillar 38, Fig. 29, Huang, similar to Darmawikarta), or it can have a curved lateral surface (pillar 38, Fig. 21, Huang). It would have been prima facie obvious to one of ordinary skill in the art to realize that these are art-recognized alternate structures for through-mold conductive pillars, and it would have been obvious to substitute the straight conductive pillar of Darmawikarta with curved conductive pillar, as shown by Huang. The use of a known structure of through-mold conductive pillar for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Rejection 2 Claim Rejections - 35 USC § 102 Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kao et al. (US 2020/0411636 A1). Re Claim 1, Kao teaches an electronic device (Fig. 1), comprising: a first electronic component (marked “110-1” in annotated Fig. 1 below, para [0014]); an encapsulant (102, Fig. 1, para [0014]) encapsulating the first electronic component (“110-1”); a first capacitor (103, Fig. 1, para [0019]) having a first depth (103 having a 1st depth, see Fig. 1) extending from an upper surface of the encapsulant (upper surface of 102); and a second capacitor (101, Fig. 1, para [0019]) having a second depth (101 having a 2nd depth, see Fig. 1), different from the first depth (2nd depth is larger than 1st depth, see Fig. 1), extending from the upper surface of the encapsulant (upper surface of 102). PNG media_image5.png 415 697 media_image5.png Greyscale Claim Rejections - 35 USC § 103 Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US 2020/0411636 A1). Re Claim 3, Kao teaches the electronic device of claim 1, further comprising: a second electronic component (marked “110-2” in annotated Fig. 1 below, para [0014]). Kao does not explicitly disclose in Fig. 1 that the second electronic component (“110-2”) have a thickness different from that of the first electronic component (“110-1”). However, Kao discloses that the electronic components 110 can be of different types for example, transistors, resistors or diodes (para [0014]). Therefore, it would be obvious to one of ordinary skill in the art that the electronic components “110-1” and “110-2” can be of different types, for example a transistor and a resistor and they will have different dimensions of widths and thicknesses. Re Claim 4, Kao teaches the electronic device of claim 3, wherein the second electronic component (“110-2”) vertically overlaps (see Fig. 1) the second capacitor (101, Fig. 1). Rejection 3 Claim Rejections - 35 USC § 103 Claims 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2015/0028450 A1), and further in view of Shibayama et al. (US 2007/0148442 A1). Re Claim 16, Park teaches an electronic device (Fig. 14B), comprising: an electronic component (412, Fig. 14B, para [0149]); an encapsulant (414, Fig. 14B, para [0149]) encapsulating the electronic component (412); and a plurality of vias (850A+850B, Fig. 14B, para [0250]) within the encapsulant (414) and configured to define a capacitor component (para [0250]). Park does not explicitly state the material for the encapsulant (414, Fig. 14B) and hence does not disclose that the encapsulant comprises a molding material and fillers within the molding material. Park states that it is an interlayer insulating layer (para [0149]). One of ordinary skill would look into related art to teach suitable materials for the interlayer insulating layer. Related art, Shibayama teaches that an interlayer insulating substrate can be made of molding materials like resin mixed with inorganic filler materials (para [0003]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the interlayer insulating layer of Park from molding materials like resin mixed with inorganic filler materials as taught by Shibayama (para [0003]). The use of a known material for making an interlayer insulating layer within a semiconductor device to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Re Claim 17, Park modified by Shibayama teaches the electronic device of claim 16, wherein the plurality of vias comprise a first electrode (444B, Fig. 14B, para [0181) and a second electrode (452B, Fig. 14B, para [0181) spaced apart from the first electrode by a dielectric layer (446B, Fig. 14B, para [0181). Re Claim 19, Park modified by Shibayama teaches the electronic device of claim 17, wherein the first electrode (444B) and the second electrode (452B) overlap a lateral surface of the encapsulant (overlaps a side surface of the encapsulant 414 within the trench, see Fig. 14B). Re Claim 20, Park modified by Shibayama teaches the electronic device of claim 16, further comprising: a carrier (470, Fig. 14B, para [0195]) supporting the encapsulant (414), wherein a first via (850A, Fig. 1B) of the plurality of vias comprises a first electrode (marked “1st electrode” in annotated Fig. 14B below, para [0181]) extending from an upper surface of the encapsulant (upper surface of 414) to the carrier (470), a second via (850B, Fig. 1B) of the plurality of vias comprises a second electrode (marked “2nd electrode” in annotated Fig. 14B below, para [0181]) extending from the upper surface of the encapsulant (upper surface of 414) to the carrier (470), and the first electrode is electrically coupled to the second electrode (“1st electrode” and “2nd electrode” are electrically coupled); and a conductive wire (454A, Fig. 14B, para [0180]) having a curved lateral surface (portion of 454A is curved, see Fig. 14B) electrically connected to the first electrode and the second electrode (“1st electrode” and “2nd electrode”). PNG media_image6.png 425 804 media_image6.png Greyscale Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al. (US 2010/0230806 A1) also teaches a similar device as the applicant (see Fig. 5). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

May 06, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740138
SEMICONDUCTOR DEVICE
3y 4m to grant Granted Sep 15, 2026
Patent 12733529
BUMP STRUCTURE AND METHOD OF MAKING THE SAME
3y 5m to grant Granted Sep 08, 2026
Patent 12727450
Semiconductor Device and Method of Forming Sacrificial Heteroepitaxy Interface to Provide Substantially Defect-Free Silicon Carbide Substrate
4y 1m to grant Granted Sep 01, 2026
Patent 12727486
WAFER MATCHING DESIGN METHOD, WAFER BONDING STRUCTURE AND CHIP BONDING STRUCTURE
3y 5m to grant Granted Sep 01, 2026
Patent 12727202
INTEGRATED CIRCUIT AND FORMATION METHOD THEREOF
3y 7m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
85%
With Interview (-1.8%)
3y 7m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 53 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month