DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Preliminary Amendment
Applicant's 5/7/2024 Preliminary Amendment to: 1. Amend the Claims is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH FINE PATTERNS.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/7/2024 and 1/30/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claims Status
Claims 1-5 and 9-19 are currently pending and being examined. Claims 6-8 and 20-25 were canceled by the 5/7/2024 Preliminary Amendment.
Claim Objections
Claim 18 is objected to because of the following informalities: The grammatical error “each pair of the word line structures”. For consistency with Claim 9, “each pair of the word line structures” will be interpreted to read as “the pair of word line structures”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5; and 9-18 are rejected under 35 U.S.C. 103 as being unpatentable over Calabrese et al (US 2022/0068722 A1, hereafter Calabrese) in view of CHANG et al (US 2023/0284431 A1, hereafter Chang) and Ramaswamy et al (US 2020/0111917 A1, hereafter Ramaswamy).
Re claim 1, Calabrese discloses in FIGS. 21-22 (with references to FIGS. 1-3 and 16) a semiconductor integrated circuit device (10a) comprising:
a target fine pattern (layout of pillars 29 of 10a as in 29 of 10 in FIG. 2; [0013]) having a first width (left-to-right extension of each pillar 29 as in FIG. 2), a first length (left-to-right extension of each pillar 29 as in FIG. 3) gradually increased (wider) toward the lower region (bottom) of the target fine pattern (layout of pillars 29 of 10a as in 29 of 10), and a first height (vertical extension of each pillar 29); and
an adjacent fine pattern (13 between pillars 29; [0013]) having contact with (physically touching as in FIG. 3; [0022]) the target fine pattern (layout of pillars 29 of 10a as in 29 of 10) along a lengthwise direction (left-to-right as in FIG. 3), the adjacent fine pattern (13 between pillars 29; [0013]) having a second width (left-to-right extension of each space for 13 as in FIG. 2), a second length (left-to-right extension of each 13 as in FIG. 3) gradually decreased (narrower) toward the lower region (bottom) of the adjacent fine pattern (13 between pillars 29), and the first height (vertical extension of each pillar 29).
Calabrese fails to disclose the first width gradually decreased toward a lower region of the target fine pattern, and the first height greater than a maximum value of the first length and a maximum value of the first width; and the second width gradually decreased toward a lower region of the adjacent fine pattern.
However,
A. Chang discloses target fine patterns (FIGS. 4A-4B; [0058]) which may be tapered (FIG. 3; [0056]-[0057]).
And,
B. Ramaswamy discloses in FIGS. 1B-1C (vertical; [0033]) and FIGS. 5A-5B (tapered; [0070]) target fine patterns with a height (H: 30-200 nm; [0033]) and a width (W: 20-200 nm; [0033]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Calabrese, as a design choices (MPEP § 42144.04), by using the taper profiles of Chang such that the first width gradually decreased toward a lower region of the target fine pattern, the second width gradually decreased toward a lower region of the adjacent fine pattern (see inserted figure below), and then applying the dimensions of Ramaswamy such that the first height is greater than a maximum value of the first length and a maximum value of the first width (see inserted figure below), changing the surface areas (Chang; [0056]) of the electrical connections without pinch-off (Ramaswamy; [0058] and [0091]) of the target fine patterns, regulating device threshold voltages.
PNG
media_image1.png
811
844
media_image1.png
Greyscale
For the record, the inserted figure (FIG. 4B of Chang rotated to represent the orientations of FIGS. 2 and 21 of Calabrese and annotated with the dimensions of Ramaswamy) depicts the first width (of TFP) gradually decreased (from UW to LW) toward a lower region of the target fine pattern (TFP), leading to the first height (H) greater than a maximum value of the first length and a maximum value of the first width; and the second width (of AFP) gradually decreased (from UW to LW) toward a lower region of the adjacent fine pattern (AFP).
Re claim 2, Calabrese and Chang and Ramaswamy disclose the semiconductor integrated circuit device of claim 1.
But, do not explicitly disclose wherein a difference between the first length of the lower region of the target fine pattern and the first length of an upper region of the target fine pattern is substantially identical to a difference between the second length of the upper region of the adjacent fine pattern and the second length of the lower region of the adjacent fine pattern.
However, by applying the dimensions of Ramaswamy, the first and second lengths could be adjusted through routine experimentation (MPEP § 2144.05) such that a difference between the first length of the lower region of the target fine pattern and the first length of an upper region of the target fine pattern is substantially identical to a difference between the second length of the upper region of the adjacent fine pattern and the second length of the lower region of the adjacent fine pattern, as part of the tapered structures discussed for claim 1.
Re claim 3, Calabrese and Chang and Ramaswamy disclose the semiconductor integrated circuit device of claim 1.
But, do not explicitly disclose wherein the first width is substantially identical to the second width.
However, by applying the dimensions of Ramaswamy, the first and second widths could be adjusted through routine experimentation (MPEP § 2144.05) such that the first width is substantially identical to the second width, as part of the tapered structures discussed for claim 1.
Re claim 4, Calabrese discloses the semiconductor integrated circuit device of claim 1, wherein the target fine pattern (layout of pillars 29 of 10a as in 29 of 10) comprises at least one of a semiconductor pattern (15; [0012]-[0013]) and a conductive pattern (30/31; [0012]-[0013]).
Re claim 5, Calabrese discloses the semiconductor integrated circuit device of claim 1, wherein the adjacent fine pattern (13) comprises an insulation pattern (13; [0013]).
Re claim 9, Calabrese discloses in FIGS. 21-22 (with references to FIGS. 1-3, 13 and 16) a semiconductor integrated circuit device (10a) comprising:
a pair of word line structures (left/right 54; [0022]) having a first height (upward extension), and extending parallelly (along the same line) in a first direction (left-to-right as in FIG. 2) divided by a recess (space along line 3-3 in FIG. 1 filled by 13/15); and
at least one active pillar (layout of pillars 29 of 10a as in 29 of 10 in FIG. 2; [0013]) and at least one device isolation pattern (insulator 13 between adjacent pillars 29; [0013]) alternately arranged in the recess (space along line 3-3 in FIG. 1 filled by 13/15) between the pair of word line structures (left/right 54).
Calabrese fails to disclose wherein the at least one active pillar has a first width gradually decreased toward a lower region of the at least one active pillar, a first length gradually increased toward the lower region of the at least one active pillar, and the first height, and wherein the at least one device isolation pattern has a second width gradually decreased toward the lower region of the at least one device isolation pattern, a second length gradually decreased toward the lower region of the at least one device isolation pattern, and the first height.
However, Chang and Ramaswamy would render these limitations obvious, changing the surface areas (Chang; [0056]) of the electrical connections without pinch-off (Ramaswamy; [0058] and [0091]) of the target fine patterns, regulating device threshold voltages, similarly as discussed for claim 1. See inserted figure above.
Re claim 10, Calabrese discloses the semiconductor integrated circuit device of claim 9, wherein the first width (left-to-right as in FIG. 2) and the second width (left-to-right extension of each space for 13 as in FIG. 2) are parallel to (overlapping) a second direction (left-to-right as in FIG. 3) substantially perpendicular (normal) to the first direction (left-to-right as in FIG. 2). For the record, the first and second widths extend in two planar directions.
But, fails to disclose the first width is substantially identical to the second width.
However, by applying the dimensions of Ramaswamy, the first and second widths could be adjusted through routine experimentation (MPEP § 2144.05) such that the first width is substantially identical to the second width, as part of the tapered structures as discussed for claim 1 (and 9).
Re claim 11, Calabrese discloses the semiconductor integrated circuit device of claim 9, wherein a direction (left-to-right) corresponding to the first length (left-to-right extension of each pillar 29 as in FIG. 3) and the second length are parallel to (overlapping) the first direction (left-to-right as in FIG. 2). For the record, the first and second lengths extend in two planar directions.
Re claim 12, Calabrese discloses the semiconductor integrated circuit device of claim 9, further comprising a gate dielectric layer (33; [0025]) interposed between the at least one active pillar (layout of pillars 29 of 10a as in 29 of 10) and the pair of word line structures (left/right 54).
Re claim 13, Calabrese discloses the semiconductor integrated circuit device of claim 9, further comprising a base layer (11; [0013]) including a plurality of bit lines (26; [0013]) and a lower insulation layer (17; [0013]), the plurality of bit lines (26) extending in a second direction (into page as in FIG. 3) substantially perpendicular (normal) to the first direction (left-to-right as in FIG. 2), and the lower insulation layer (17) configured (between; [0013]) to electrically isolate (separate) the plurality of bit lines (26) from each other.
Re claim 14, Calabrese discloses the semiconductor integrated circuit device of claim 13, wherein a part of the plurality of bit lines (26) is exposed through the recess (space along line 3-3 in FIG. 1 filled by 13/15) and the at least one active pillar (layout of pillars 29 of 10a as in 29 of 10) is formed on the exposed part of the plurality of bit lines through the recess (space along line 3-3 in FIG. 1 filled by 13/15).
Re claim 15, Calabrese discloses the semiconductor integrated circuit device of claim 14, further comprising: a drain (30; [0013]) formed in a lower region (bottom) of the at least one active pillar (layout of pillars 29 of 10a as in 29 of 10) adjacent to (on) each bit line (26); and a source (32; [0013]) formed in an upper region (top) of the at least one active pillar (layout of pillars 29 of 10a as in 29 of 10).
Re claim 16, Calabrese discloses the semiconductor integrated circuit device of claim 15, further comprising a capacitor electrode (of 85; [0025]) formed on (coupled to; [0025]) the source (32).
Re claim 17, Calabrese discloses the semiconductor integrated circuit device of claim 16, wherein an ohmic contact layer (31; [0013]) is formed between each bit line and the drain and/or the capacitor electrode (of 85) and the source (32).
Re claim 18, Calabrese discloses the semiconductor integrated circuit device of claim 15, wherein the pair of word line structures (left/right 54) comprises: a first insulating interlayer (45a; [0024]) formed on the base layer (11); a word line conductive layer (gate conductive material; [0022]) formed on the first insulating interlayer (45a).
But, fails to explicitly disclose a second insulating interlayer formed on the word line conductive layer (gate conductive material).
However, Calabrese discloses in the embodiment of FIG. 13 a second insulating interlayer (upper 45; [0017]) formed on the word line conductive layer (conductive gate line; [0036]). Thus, it would have been obvious to one of ordinary skill in the art to use the second insulating interlayer formed on the word line conductive layer with the embodiment of FIG. 21 as an alternative structure for protectively isolating word line conductive layers and providing first and second gate dielectric layers of different compositions, the second gate dielectric layer material has lower intrinsic k (dielectric constant that is material-intrinsic) than first gate dielectric layer material, for minimizing gate-induced-drain-leakage (GIDL; [0017]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Calabrese and Chang and Ramaswamy as applied to claim 18 above, and further in view of Kang et al (US 2002/0084500 A1, hereafter Kang).
Re claim 19, Calabrese and Chang and Ramaswamy disclose the semiconductor integrated circuit device of claim 18.
But, fail to disclose wherein the word line conductive layer (Calabrese: left/right 54) comprises: a first work function layer formed on the first insulating interlayer and positioned adjacent to the drain; a second work function layer formed on the first work function layer; and a third work function layer formed on the second work function layer, wherein the second work function layer has a work function higher than a work function of at least one of the first and third work function layers.
However,
Kang discloses in FIG. 2 a semiconductor memory device comprising: a word line conductive layer (113; [0041]) comprising: a first work function layer (poly-silicon; [0041]), a second work function (tungsten; [0041]) layer formed on the first work function layer (poly-silicon); and a third work function layer (poly-silicon; [0041]) formed on the second work function layer (tungsten), wherein the second work function layer (tungsten) has a work function higher (4.32 eV - 5.22 eV) than a work function (~4.05 eV - 4.7 eV) of at least one of the first and third work function layers (poly-silicon).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Calabrese, by using the word line conductive layer materials of Kang for the word line conductive layer of Calabrese, where a first work function layer is formed on the first insulating interlayer and positioned adjacent to the drain; a second work function layer is formed on the first work function layer; and a third work function layer is formed on the second work function layer, wherein the second work function layer has a work function higher than a work function of at least one of the first and third work function layers, so that the formation first and second insulating interlayers can be smoothly performed on the word line conductive layer (Kang; [0041]), for the expected results of providing a gate (word line) electrode for controlling transistor channel currents.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20080105878 A1 discloses polysilicon/tungsten/polysilicon conductive layers used in memory devices.
US 20240032278 A1 discloses polysilicon/tungsten conductive layers used in memory devices with tapered patterns.
Current efforts in the development of advanced 3D memory structures include smaller sizes and high aspect ratios without degrading electrical characteristics of the memory component(s).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC W JONES/Primary Examiner, Art Unit 2892
Prosecution Insights