Prosecution Insights
Last updated: October 02, 2026
Application No. 18/656,613

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102
Filed
May 07, 2024
Priority
Oct 17, 2023 — RE 10-2023-0138532
Examiner
PHAM, THANHHA S
Art Unit
Tech Center
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
761 granted / 891 resolved
+25.4% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
16 currently pending
Career history
904
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
40.1%
+0.1% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
24.8%
-15.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 891 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of figs. 3 and 6, claims 1-3, 6, and 8-11 without traverse in the reply filed on 07/15/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guo et al [US 2024/0215257]. ► With respect to claim 1, Guo e al (fig 8, text [0001]-[0094]) discloses a semiconductor device comprising: a first semiconductor structure including a cell region (102, text [0039]) and a peripheral circuit region (130, text [0064]), a cell capacitor (112, text [0040]) disposed in the cell region, and a first insulating layer (404, text [0081]) disposed in the cell region and the peripheral circuit region to cover the cell capacitor; a second semiconductor structure (402, text [0078]) including a cell transistor (106, text [0039]) disposed over the first insulating layer in the cell region and a peripheral circuit transistor disposed over the first insulating layer in the peripheral circuit region; and a first conductor (108, text [0039]) passing through the first insulating layer to electrically connect a first cell source/drain region (text [0065]) of the cell transistor and an electrode of the cell capacitor. ► With respect to claim 6, Guo e al discloses wherein a lower surface of the first cell source/drain region (text [0065]) contacts the first conductor (108, text [0039]). Allowable Subject Matter Claims 2-3, and 8-11 are objected. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANHHA S PHAM whose telephone number is (571)272-1696. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THANHHA S PHAM/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 07, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12733478
SELECTIVE BOTTOMLESS GRAPHENE LINED INTERCONNECTS
4y 2m to grant Granted Sep 08, 2026
Patent 12727229
EXTENDED SOURCE/DRAIN CONTACT FOR SHIFTED DRAIN VOLTAGE FOR A BACKSIDE POWER DISTRIBUTION NETWORK
3y 8m to grant Granted Sep 01, 2026
Patent 12727187
INTEGRATED CIRCUIT WITH PATTERN OVERLAY FOR ASSISTING OVERLAY SIGNAL AND ACCURACY
2y 11m to grant Granted Sep 01, 2026
Patent 12720778
INTEGRATED CIRCUITS WITH HIGH DIELECTRIC CONSTANT INTERFACIAL LAYERING
4y 11m to grant Granted Aug 25, 2026
Patent 12720761
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
3y 8m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
90%
With Interview (+4.8%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 891 resolved cases by this examiner. Grant probability derived from career allowance rate.

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