DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/7/2024 and 1/21/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 and 7 rejected under 35 U.S.C. 103 as being unpatentable over Chan et.al. (US-20030235958A1, hereinafter Chan), and further in view of Williams et.al. (US-20040173844A1, hereinafter Williams)
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Regarding Claim 1.
Chan teaches in Fig.4 and in related text A semiconductor device, comprising:
an epitaxial layer (#13/#43 N-type) having a first conductive type;
a gate structure (#14/#15/#44) disposed in the epitaxial layer and having a curved surface protruding into the epitaxial layer (#43),
a well (#12, P-type) disposed in the epitaxial layer and having a second conductive type different from the first conductive type, wherein the well extends into the epitaxial layer (#43) along the curved surface of the gate structure and the well (#12) is in contact with the curved surface; and
a source electrode (#17) disposed above the epitaxial layer (#43) and electrically connected to the well (#12).
Chan does not explicitly disclose wherein a breadth depth ratio of the gate structure is less than or equal to 1;
However, Williams teaches wherein a breadth depth ratio of the gate structure is less than or equal to 1; (William [0077-0078] #438 with depth of 1-2um and width from 1um down to 0.35um, thus the disclosed rations are <= 1.)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Chan’s semiconductor device with the teachings of Williams, as identified above, as this design merely select known dimensions for an otherwise conventional active gate trench and predictably produces a gate breadth/depth ration <=1 without changing the device’s principle of operation.
Regarding Claim 6.
Chan modified by Williams teaches The semiconductor device according to claim 1, Chan further teaches wherein the curved surface of the gate structure (#44/#14/#45) extends upward and is connected to a top surface of the epitaxial layer. (corner region #45 extended upward and is connected to #43)
Regarding Claim 7.
Chan modified by Williams teaches The semiconductor device according to claim 1, Chan further teaches in Fig.4 wherein a depth of a bottom surface of the well (#12) is greater than a maximum depth of the curved surface of the gate structure (#44/#14/#45).
Claims 2 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et.al. (US-20030235958A1, hereinafter Chan), in view of Williams et.al. (US-20040173844A1, hereinafter Williams), and further in view of Hshieh et. al. (US-5929481-A, hereinafter Hshieh)
Regarding Claim 2.
Chan modified by Williams teaches The semiconductor device according to claim 1, Hshieh teaches in Fig.2 further comprising a heavily doped region (#57), wherein the well (#56) is disposed between the gate structure (#64/#66) and the heavily doped region (#57), the heavily doped region has a doping concentration greater than a doping concentration of the well, and a depth of the heavily doped region is greater than a depth of the well. (#57 with a depth deeper than #56)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Chan and Williams with the teachings of Hshieh, as identified above, in order to improve the reliability by relocating avalanche breakdown away from the trench bottom and protecting the trench region.
Regarding Claim 4 and 5.
Chan modified by Williams and Hshieh teaches The semiconductor device according to claim 2,
Hshieh further teaches
(claim 4) further comprising a source region (#58) having the first conductive type (N-type) and disposed between the gate structure (#64/#66) and the heavily doped region (#57).
(claim 5) wherein the well (#56) is below the source region (#58).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Chan, Williams and Hshieh with the teachings of Hshieh, as identified above, as this would continue to perform their established functions, with the predictable result and to improve the reliability of the device .
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chan et.al. (US-20030235958A1, hereinafter Chan), in view of Williams et.al. (US-20040173844A1, hereinafter Williams), and further in view of Darwish et.al. (US-2006/0038223-A1, hereinafter Darwish)
Regarding 8.
Chan modified by Williams teaches The semiconductor device according to claim 1,
Chan modified by Williams teaches in Fig.4 the curved bottom surface of the gate structure and a bottom surface of the gate structure is less than the depth of the bottom surface of the well but does not explicitly disclose
wherein the gate structure comprises a gate electrode and a maximum depth of a bottom surface of the gate electrode is less than the depth of the bottom surface of the well.
Darwish teaches in Fig.16 and Fig.5H
wherein the gate structure comprises a gate electrode (Fig.5H #53) and a maximum depth of a bottom surface of the gate electrode is less than the depth of the bottom surface of the well. ([0065] A polysilicon layer 53 is then deposited over the gate oxide layer 39, filling the trench 35 (FIG. 5H). In an N-channel MOSFET polysilicon layer 53 is typically doped with phosphorus to a concentration of 5×1019 cm−3. also [0069] Fig.16 the P body diffusion may be driven to a level below the bottom of the trench but above the interface between the epi layer and the substrate, as evidenced by P body 128 in FIG. 19.)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Chan and Williams with the teachings of Darwish, as identified above, in order to move the relevant body junction and high-field breakdown region away from the trench corner and gate oxide, thereby improving the implantation and drive-in depth of the body dopant, with the predictable result and to improve the reliability of the device .
Claims 9-10, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over TW139 (TW-202406139-A, hereinafter TW139), in view of Williams et.al. (US-20040173844-A1, hereinafter Williams)
Regarding Claim 9.
TW139 teaches in Fig 6 and in related text, A method of forming a semiconductor device, comprising:
forming an epitaxial layer (#103) on a substrate (#101), wherein the epitaxial layer has a first conductive type (#103 has a first conductivity type such as N-type);
performing a first implantation process to form a well (#116) in the epitaxial layer and having a second conductive type different from the first conductive type (#!16 has a second conductivity type such as P-type);
performing a second implantation process to form a source region (#118) in the epitaxial layer and having the first conductive type (#118 has the first conductivity type, such as N-type), wherein the source region is disposed on the well;
removing a portion of the epitaxial layer, the well, and the source region to form a curved groove (#106 curved trench) that is concave inward the epitaxial layer and exposes the well; and
forming a gate structure (#110/#109/#107) in the curved groove, wherein the gate structure has a curved surface contacting the curved groove,
TW139 does not explicitly disclose and a breadth depth ratio of the gate structure is less than or equal to 1.
However, Williams teaches wherein a breadth depth ratio of the gate structure is less than or equal to 1; (William [0077-0078] #438 with depth of 1-2um and width from 1um down to 0.35um, thus the disclosed rations are <= 1.)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify TW139’s semiconductor device with the teachings of Williams, as identified above, as this design merely select known dimensions for an otherwise conventional active gate trench and predictably produces a gate breadth/depth ration <=1 without changing the device’s principle of operation.
Regarding Claim 10.
TW139 modified by Williams teaches The method according to claim 9,
TW139 further teaches in Fig.6-9 further comprising:
performing a third implantation process to form a heavily doped region in the epitaxial layer (#120-1, #120-2) and having the second conductive type (#120 has the second conductivity type, such as P-type),
wherein the well (#116) is disposed between the heavily doped region (#120) and the gate structure (#109/#110/#107), and a doping concentration of the heavily doped region is greater than a doping concentration of the well.
Regarding Claim 12.
TW139 modified by Williams teaches in Fig 6-9 The method according to claim 9, TW139 further teaches wherein the curved surface of the gate structure (#110/#109/#107) extends upward and is connected to a top surface of the epitaxial layer (#103).
Regarding Claim 14.
TW139 modified by Williams teaches in Fig 6-9 The method according to claim 9, TW139 further teaches wherein the gate structure (#110/#109/#107) is formed in the curved groove such that the gate structure fills the curved groove (#106) and the gate structure is in contact with the well (#116) and the source region (#118).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over TW139 (TW-202406139-A, hereinafter TW139), in view of Williams et.al. (US-20040173844A1, hereinafter Williams), and further in view of Hshieh et. al. (US-5929481-A, hereinafter Hshieh)
Regarding Claim 11.
TW139 modified by Williams teaches The method according to claim 10,
Hshieh teaches in Fig.2 wherein a depth of the heavily doped region (#57) is greater than a depth of the well (#56).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of TW139 and Williams with the teachings of Hshieh, as identified above, in order to improve the reliability by relocating avalanche breakdown away from the trench bottom and protecting the trench region. This is a known adjustment of the body-contact implantation profile with predictable result.
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over TW139 (TW-202406139-A, hereinafter TW139), in view of Williams et.al. (US-20040173844A1, hereinafter Williams), and further in view of Darwish et.al. (US-2006/0038223-A1, hereinafter Darwish)
Regarding Claim 13 and 15.
TW139 modified by Williams teaches The method according to claim 9,
TW139 modified by Williams teaches the curved bottom surface of the gate structure but does not explicitly disclose
(claim 13) wherein a depth of a bottom surface of the well is greater than a maximum depth of the bottom surface of the gate structure. And
(clam 15) wherein the gate structure comprises a gate electrode and a maximum depth of a bottom surface of the gate electrode is less than the depth of the bottom surface of the well.
Darwish teaches in Fig.16 and Fig.5H
(Claim 13) wherein a depth of a bottom surface of the well (#128) is greater than a maximum depth of the bottom surface of the gate structure. ([0069] Fig.16 the P body diffusion may be driven to a level below the bottom of the trench but above the interface between the epi layer and the substrate, as evidenced by P body 128 in FIG. 19.)
(claim 15) wherein the gate structure comprises a gate electrode (Fig.5H #53) and a maximum depth of a bottom surface of the gate electrode is less than the depth of the bottom surface of the well. ([0065] A polysilicon layer 53 is then deposited over the gate oxide layer 39, filling the trench 35 (FIG. 5H). In an N-channel MOSFET polysilicon layer 53 is typically doped with phosphorus to a concentration of 5×1019 cm−3. )
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of TW139 and William with the teachings of Darwish, as identified above, in order to move the relevant body junction and high-field breakdown region away from the trench corner and gate oxide, thereby improving the implantation and drive-in depth of the body dopant, with the predictable result and to improve the reliability of the device .
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein the well does not extend to a lowest point of the curved surface, such that the well has an opening, and a width of the opening is less than 80% of a width of the gate structure. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817