DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, species A, claims 1-10 in the reply filed on 07/30/2026 is acknowledged.
Specification
The disclosure is objected to because of the following informalities: p. 8, line 8, semicondcuto should read semiconductor. Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. US 10,741,414.
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Yamazaki et al. US 10,741,414
Regarding claim 1, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67 disclose a thin film transistor 50 comprising:
a gate electrode 61 col. col. 56, lines 43-67 disposed on a substrate 51;
a semiconductor layer 55 overlapping the gate electrode 61 via a gate insulating layer 59 interposed therebetween; and
a source electrode 57 and a drain electrode 58 in contact with the semiconductor layer 55,
wherein the semiconductor layer 55 col. 59, lines 24-26 and col. 17, lines 42-57 includes an amorphous oxide semiconductor, and
wherein the semiconductor layer 55 col. 59, lines 24-26 and col. 17, lines 42-57 includes nanocrystalline dots (Note that the oxide semiconductor film 17 may be a mixed film including two or more of the following: a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region of CAAC-OS described later, and a region having a single-crystal structure. The mixed film has a single-layer structure including, for example, two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a CAAC-OS region, and a region having a single-crystal structure in some cases.).
Regarding claim 2, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67 disclose the thin film transistor of claim 1, wherein: the semiconductor layer 55 (annotated above) includes a channel region, and a source region and a drain region disposed in both sides of the channel region, the channel region overlaps the gate electrode 61, and the source region and the drain region are connected to the source electrode 57 and the drain electrode 58.
Regarding claim 3, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67 disclose the thin film transistor of claim 1, wherein:
the semiconductor layer 55 col. 59, lines 24-26, col. 17, lines 42-57 and col. 75, lines 1-30 includes at least one of IGO (Indium-Gallium Oxide), IGZO (Indium-Gallium-Zinc Oxide), IZTO (Indium-Zinc-Tin Oxide), IGZTO (Indium-Gallium-Zinc- Tin Oxide).
Regarding claim 4, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67, col. 59, lines 24-26, col. 17, lines 42-57 and col. 75, lines 1-30 disclose the thin film transistor of claim 3, wherein: the nanocrystalline dots of the semiconductor layer 55 include indium (In).
Regarding claim 5, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67, col. 59, lines 24-26, col. 17, lines 42-57 and col. 75, lines 1-30 disclose the thin film transistor of claim 4, wherein: the nanocrystalline dots of the semiconductor layer 55 include indiumoxide (In2O3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. US 10,741,414.
Regarding claim 6, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67, col. 59, lines 24-26, col. 17, lines 42-57 and col. 75, lines 1-30 disclose the thin film transistor of claim 3, but does not expressly disclose wherein: a ratio of the nanocrystalline dots to the semiconductor layer is about 10% or less.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 7, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67, col. 59, lines 24-26, col. 17, lines 42-57 and col. 75, lines 1-30 disclose the thin film transistor of claim 6, but does not expressly disclose wherein: the ratio of the nanocrystalline dots to the semiconductor layer is less than 8%.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 8, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67 disclose the thin film transistor of claim 1 but does not expressly disclose wherein: a mass density of the semiconductor layer is about 5.5g/cm3 to about 7.5g/cm3.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 9, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67 disclose the thin film transistor of claim 8 but does not expressly disclose wherein: the mass density of the semiconductor layer is about 6g/cm3 to about 7g/cm3.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 10, Yamazaki et al. Fig. 38B, col. col. 56, lines 43-67 disclose the thin film transistor of claim 1 but does not expressly disclose wherein: at least portion of the semiconductor layer is treated with nitrous oxide(N2O) plasma.
However, the claim limitation “wherein: at least portion of the semiconductor layer is treated with nitrous oxide (N2O) plasma” is drawn to a product by process.
"[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See, for example, MPEP 2113.I.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
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