DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant’s amendments filed on 6/25/2026 have been entered.
Election/Restriction
Applicant’s election of Group I, Claims 1-16, drawn to a method, without traverse, has been acknowledged. Claims 1-16 and 21-24 remain pending. Claims 17-20 were cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 10, and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (US 2022/0384610) in view of Mulfinger et al (US 2019/0221483).
Regarding Claim 1, Liu et al discloses a method (method 100 [0017]), comprising: receiving a structure (workpiece 200 [0018] Fig 2-19) comprising:
a fin-shaped active region (fin-shaped structure 212 [0021] Fig 3) over a substrate (substrate 202 [0021] Fig 3) and comprising a plurality of channel layers (channel layers 208 [0018] Fig 3) interleaved by a plurality of sacrificial layers (sacrificial layers 206 [0018] Fig 3), and
a dummy gate stack (dummy gate stack 220 [0022] Fig 4) over a channel region (channel region 212C [0035] Fig 5-15) of the fin-shaped active region (212 Fig 3),
removing (shown in Fig 5) a source/drain region (source/drain regions 212SD [0025] Fig 5) of the fin-shaped active region (212 Fig 3) to form a source/drain opening (source/drain trenches 228 [0025] Fig 6);
performing an etching process (selective dry etching process [0026] Fig 7) to selectively recess the plurality of sacrificial layers (206 Fig 7) to form inner spacer recesses (inner spacer recess 230 are formed [0026] Fig 7);
forming inner spacer features (inner spacer features 240 [0027] Fig 9) in the inner spacer recesses (230 Fig 7);
forming a source/drain feature (source/drain features 242 [0027] Fig 10) in the source/drain opening (228 Fig 9);
selectively removing (dummy gate stack is removed [0034]) the dummy gate stack (220 Fig 11) to form a gate trench (gate trench 248 [0034] Fig 12);
selectively removing (selectively removed [0035]) the plurality of sacrificial layers (206’ Fig 12) to form a plurality of gate openings (first openings 249 [0035] Fig 13); and
forming a gate structure (gate structure 250 [0040] Fig 15/250a [0043] Fig 16) in the gate trench (248 Fig 14) and the plurality of gate openings (249 Fig 13, 249’ Fig 14/250a [0043] Fig 16), wherein the gate structure (250 Fig 15).
Liu et al does not disclose
a first portion formed in a first gate opening of the plurality of gate openings and a second portion formed in a second gate opening of the plurality of gate openings,
a gate length of the first portion is different from a gate length of the second portion.
Mulfinger et al, in the related art of semiconductor devices that include FET devices, discloses
a first portion (first portion of functional metal layers 800 [0083] shown in annotated Fig 6) formed in a first gate opening (area where 800 is present shown in Fig 6) of the plurality of gate openings (area where 800 is present shown in Fig 6) and a second portion (second portion of functional metal layers 800 [0083] shown in annotated Fig 6) formed in a second gate opening (area where 800 is present shown in Fig 6) of the plurality of gate openings (area where 800 is present shown in Fig 6),
a gate length of the first portion (first portion of 800 shown in annotated Fig 6) is different from a gate length of the second portion (second portion of 800 shown in annotated Fig 6).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu et al to include a first portion formed in a first gate opening of the plurality of gate openings and a second portion formed in a second gate opening of the plurality of gate openings, a gate length of the first portion is different from a gate length of the second portion as taught by Mulfinger et al in order to simultaneously function as an etch barrier that supports the epitaxial source/drain region during the etching process [0071], and optimize the electrical function capability of the device. Further, a person of ordinary skill in the art would have recognized that protecting the source/drain region during the etching process would improve the quality and reliability of the resulting device (see MPEP 2143.I(D)).
Regarding Claim 2, the combination of Liu et al and Mulfinger et al discloses the limitations of claim 1 as explained above. The combination of Liu et al and Mulfinger et al further discloses
wherein a gate length of a portion (second portion of 800 shown above in annotated Fig 6 Mulfinger et al) of the gate structure (800 Fig 6 Mulfinger et al) formed in the gate trench (area where 800 is present Fig 6 Mulfinger et al) is less than the gate length of the first portion (first portion of 800 shown in annotated Fig 6 Mulfinger et al).
Regarding Claim 3, the combination of Liu et al and Mulfinger et al discloses the limitations of claim 1 as explained above. The combination of Liu et al and Mulfinger et al further discloses
wherein the first gate opening (area where the first portion of 800 is present shown above in annotated Fig 6 Mulfinger et al) is disposed under the second gate opening (area where the second portion of 800 is present shown above in annotated Fig 6 Mulfinger et al), and the gate length of the first portion (first portion of 800 shown in annotated Fig 6 Mulfinger et al) is greater than the gate length of the second portion (second portion of 800 shown in annotated Fig 6 Mulfinger et al).
Regarding Claim 4, the combination of Liu et al and Mulfinger et al discloses the limitations of claim 1 as explained above. The combination of Liu et al and Mulfinger et al further discloses
wherein the plurality of sacrificial layers (epitaxial silicon germanium layers/sacrificial layers 211, 212, 213, 221, 222, 223, 224 [0029] Fig 1 Mulfinger et al) comprise a bottommost sacrificial layer (211 Fig 1 Mulfinger et al) and a topmost sacrificial layer (224 Fig 1 Mulfinger et al) over the bottommost sacrificial layer (211 Fig 1 Mulfinger et al), and a germanium concentration of the topmost sacrificial layer (a fourth low-germanium silicon germanium layer 224 [0048] Fig 1 Mulfinger et al) is different than a germanium concentration of the bottommost sacrificial layer (first high-germanium content SiGe layer 211 [0043] Fig 1 Mulfinger et al).
Regarding Claim 5, the combination of Liu et al and Mulfinger et al discloses the limitations of claim 4 as explained above. The combination of Liu et al and Mulfinger et al further discloses
wherein the etchant of the etching process etches the top most layer (224 Fig 1 Mulfinger et al) at a rate higher than it etches the bottom most layer (211 Fig 1 Mulfinger et al) (a selective etch may include an etch chemistry that removes a first material selectively to a second material by a ratio of 2:1 or greater [0080] Mulfinger et al).
Regarding Claim 6, the combination of Liu et al and Mulfinger et al discloses the limitations of claim 4 as explained above. The combination of Liu et al and Mulfinger et al further discloses
wherein the selectively removing of the bottommost sacrificial layer (211 Fig 1 Mulfinger et al) and the topmost sacrificial layer (224 Fig 1 Mulfinger et al) of the plurality of sacrificial layers forms the first gate opening (shown in annotated Fig 6 Mulfinger et al) and the second gate opening (shown in annotated Fig 6 Mulfinger et al) respectively, and
the second gate opening (shown in annotated Fig 6 Mufinger et al) spans a width greater than the first gate opening (shown in annotated Fig 6 Mulfinger et al).
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Regarding Claim 10, Liu et al discloses a method (method 100 [0017]), comprising: forming a first sacrificial layer (bottom sacrificial layer 206 [0018] Fig 3) over a substrate (substrate 202 [0021] Fig 3);
forming a first channel layer (bottom channel layer 208 [0018] Fig 3) over the first sacrificial layer (bottom sacrificial layer 206 [0018] Fig 3);
forming a second sacrificial layer (middle 206 Fig 3) over the first channel layer (bottom 208 Fig 3),
forming a second channel layer (middle 208 Fig 3) over the second sacrificial layer (middle 206 Fig 3);
performing a first etching (selective dry etching process [0026] Fig 7) process;
after the performing of the first etching process (selective dry etching process [0026]),
performing a second etching process (selective dry etch [0035]) to selectively remove (selectively removed [0035]) the laterally recessed first sacrificial layer (bottom 206’ Fig 12) and the second sacrificial layer (middle 206’ Fig 12) to form a first gate opening (bottom first opening 249 [0035] Fig 13) and a second gate opening (middle first opening 249 [0035] Fig 13); and
forming a gate structure (gate structure 250 [0043] Fig 15/inner portion of gate structure 150a [0043] Fig 16)) in the first gate opening (bottom 249 Fig 13) and the second gate opening (middle 249 Fig 13).
Liu et al does not directly disclose
wherein the first sacrificial layer and the second sacrificial layer comprise different compositions;
performing a first etching process to laterally recess the first sacrificial layer and the second sacrificial layer at different etch rates.
Mulflinger et al, in the related art of semiconductor devices that include FET devices, discloses
wherein the first sacrificial layer (first high-germanium content SiGe layer 211 [0043]/may be sacrificial layers [0029] Fig 1) and the second sacrificial layer (first low-germanium content SiGe layer 221 [0043]/may be sacrificial layers [0029] Fig 1) comprise different compositions; and
performing a first etching process (selective etch [0068]) to laterally recess the first sacrificial layer (211 Fig 1) and the second sacrificial layer (221 Fig 1) at different etch rates (different rate of removal [0080]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu et al to include wherein the first sacrificial layer and the second sacrificial layer comprise different compositions; and performing a first etching process to laterally recess the first sacrificial layer and the second sacrificial layer at different etch rates as taught by Mulfinger et al in order to remove a first material selectively to a second material by a different ratio [0080]. Further, a person of ordinary skill in the art would have recognized that having different etch rates would allow for more control over the selective removal process which would improve the quality of the resulting device elements formed (see MPEP 2143.I(D)).
Regarding Claim 21, Liu et al discloses a method (method 100 [0017]), comprising:
forming active region (fin-shaped structure 212 [0021] Fig 3) over a substrate (substrate 202 [0021] Fig 3) and extending lengthwise along a first direction (horizontal direction Fig 3), the active region (212 Fig 3) comprising a plurality of channel layers (channel layers 208 [0018] Fig 3) interleaved by a plurality of sacrificial layers (sacrificial layers 206 [0018] Fig 3),
forming an isolation feature (isolation feature 214 [0021] Fig 3) disposed alongside the active region (212 Fig 3);
forming a trench (gate trench 248 [0034] Fig 12) extending through the active region (212 Fig 3);
performing an etching process (selective dry etching process [0026] Fig 7) to recess the plurality of sacrificial layers (206 Fig 3),
epitaxially growing a source/drain feature (source/drain features 242 [0027] Fig 10) in the trench (248 Fig 12);
after the performing of the etching process (selective dry etching process [0026] Fig 7), selectively removing (selectively removed [0035]) remaining portions of the plurality of sacrificial layers (206’ Fig 12); and
forming a gate structure (gate structure 250 [0040] Fig 15/250a/b [0043] Fig 16) over the active region (212 Fig 12) and extending lengthwise along a second direction (vertical direction Fig 3) different from the first direction (horizontal Fig 3), wherein the gate structure (250 Fig 15/250a/b Fig 16) wraps around the plurality of channel layers (208 Fig 3).
Liu et al does not directly disclose
wherein a composition of a bottommost sacrificial layer of the plurality of sacrificial layers is different from a composition of a topmost sacrificial layer of the plurality of sacrificial layers;
wherein the etching process recesses the topmost sacrificial layer at a first etch rate and recesses the bottommost sacrificial layer at a second etch rate different from the first etch rate.
Mulflinger et al, in the related art of semiconductor devices that include FET devices, discloses
wherein the first sacrificial layer (first high-germanium content SiGe layer 211 [0043]/may be sacrificial layers [0029] Fig 1) and the fourth sacrificial layer (a fourth low-germanium silicon germanium layer 224 [0048] Fig 1 Mulfinger et al) comprise different compositions; and
performing a first etching process (selective etch [0068]) to laterally recess the first sacrificial layer (211 Fig 1) and the fourth sacrificial layer (224 Fig 1) at different etch rates (different rate of removal [0080]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu et al to include wherein a composition of a bottommost sacrificial layer of the plurality of sacrificial layers is different from a composition of a topmost sacrificial layer of the plurality of sacrificial layers wherein the etching process recesses the topmost sacrificial layer at a first etch rate and recesses the bottommost sacrificial layer at a second etch rate different from the first etch rates as taught by Mulfinger et al in order to remove a first material selectively to a second material by a different ratio [0080]. Further, a person of ordinary skill in the art would have recognized that having different etch rates would allow for more control over the selective removal process which would improve the quality of the resulting device elements formed (see MPEP 2143.I(D)).
Regarding Claim 22, the combination of Liu et al and Mulfinger et al discloses the limitations of claim 21 as explained above. The combination of Liu et al and Mulfinger et al further discloses
wherein the plurality of sacrificial layers (epitaxial silicon germanium layers/sacrificial layers 211, 212, 213, 221, 222, 223, 224 [0029] Fig 1 Mulfinger et al) comprise a bottommost sacrificial layer (211 Fig 1 Mulfinger et al) and a topmost sacrificial layer (224 Fig 1 Mulfinger et al) over the bottommost sacrificial layer (211 Fig 1 Mulfinger et al), and a germanium concentration of the topmost sacrificial layer (a fourth low-germanium silicon germanium layer 224 [0048] Fig 1 Mulfinger et al) is different than a germanium concentration of the bottommost sacrificial layer (first high-germanium content SiGe layer 211 [0043] Fig 1 Mulfinger et al).
Regarding Claim 23, the combination of Liu et al and Mulfinger et al discloses the limitations of claim 21 as explained above. The combination of Liu et al and Mulfinger et al further discloses
wherein the first etch rate is greater than the second etch rate (a selective etch may include an etch chemistry that removes a first material selectively to a second material by a ratio of 2:1 or greater [0080] Mulfinger et al).
Regarding Claim 24, the combination of Liu et al and Mulfinger et al discloses the limitations of claim 21 as explained above. The combination of Liu et al and Mulfinger et al further discloses
wherein the gate structure (gate structure 250 [0040] Fig 15/250a/b [0043] Fig 16 Liu et al) comprises:
a first portion (shown in annotated Fig 16 Liu et al) disposed under a bottommost channel layer (portions 2082, 2084, 2086 of channel 2080 [0045] Fig 16 Liu et al) of the plurality of channel layers (channel layers 208 [0018] Fig 3 Liu et al),
a second portion (shown in annotated Fig 16 Liu et al) disposed directly under a topmost channel layer (topmost channel member 2080T [0045] Fig 16 Liu et al) of the plurality of channel layers (channel layers 208 [0018] Fig 3 Liu et al), and
a third portion (shown in annotated Fig 16 Liu et al) disposed over the plurality of channel layers (channel layers 208 [0018] Fig 3 Liu et al).
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The combination of Liu et al and Mulfinger et al, as applied to claim 21, does not directly disclose
wherein a dimension of the first portion is greater than a dimension of the second portion, and the dimension of the second portion is greater than the dimension of the third portion.
Mulflinger et al, in the related art of semiconductor devices that include FET devices, discloses
wherein a dimension of the first portion (shown in annotated Fig 6) is greater than a dimension (in alternate embodiments, a width of the remaining portions of sacrificial may be greater than the width of the sacrificial gate [0069]) of the second portion (shown in annotated Fig 6), and the dimension of the second portion (shown in annotated Fig 6) is greater than the dimension of the third portion (shown in annotated Fig 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Liu et al and Mulfinger et al, as applied to claim 21, to include wherein a dimension of the first portion is greater than a dimension of the second portion, and the dimension of the second portion is greater than the dimension of the third portion as taught by Mulfinger et al as a result of having more control over the etching process when sacrificial layers function as an etch barrier [0071]. Further, a person of ordinary skill in the art would have recognized that having more control over the etching process would be advantageous in increasing the efficiency of fabrication while improving the quality of the resulting device (see MPEP 2143.I(D)).
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Allowable Subject Matter
Claims 7-9 and 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7: The prior art does not anticipate or render obvious, alone or in combination, that “herein the structure further comprises a gate spacer extending along a sidewall surface of the dummy gate stack, wherein a width of the gate spacer is greater than a width of a widest inner spacer feature of the inner spacer features,” in the combination required by the claim.
Specifically, the combination of Liu et al and Mulfinger et al does not disclose these limitations, as shown in Fig 15 of the instant application, as shown below. Further, should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references to modify the combination of Liu et al and Mulfinger et al.
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It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 8: The prior art does not anticipate or render obvious, alone or in combination, that “before the forming of the source/drain feature, forming a dielectric layer to fill a bottom portion of the source/drain opening, wherein the source/drain feature is over and in direct contact with the dielectric layer,” in the combination required by the claim.
Specifically, the combination of Liu et al and Mulfinger et al does not disclose these limitations, as shown in Fig 15 of the instant application, as shown below. Further, should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references to modify the combination of Liu et al and Mulfinger et al.
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It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 9: The prior art does not anticipate or render obvious, alone or in combination, that “further comprising: forming a dielectric layer between and in direct with the substrate and the gate structure,” in the combination required by the claim.
Specifically, the combination of Liu et al and Mulfinger et al does not disclose these limitations, as shown in Fig 15 of the instant application, as shown below. Further, should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references to modify the combination of Liu et al and Mulfinger et al.
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It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 11: The prior art does not anticipate or render obvious, alone or in combination, that “wherein the first sacrificial layer and the second sacrificial layer comprise silicon germanium, and a germanium concentration of the second sacrificial layer is higher than a germanium concentration of the first sacrificial layer,” in the combination required by the claim.
Specifically, the combination of Liu et al and Mulfinger et al does not disclose these limitations, as shown in Fig 13 of the instant application, as shown below. Further, should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references to modify the combination of Liu et al and Mulfinger et al.
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It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 12-13 would be allowable based on their dependency on Claim 11.
Claim 14: The prior art does not anticipate or render obvious, alone or in combination, that “further comprising: forming a third sacrificial layer over the second channel layer, wherein the first sacrificial layer and the third sacrificial layer comprise a same material but different constituent atomic percentages; and forming a third channel layer over the third sacrificial layer, wherein the performing of the first etching process further laterally recesses the third sacrificial layer, wherein the performing of the second etching process further selectively removes the laterally recessed third sacrificial layer, thereby forming a third gate opening, wherein the gate structure is further formed in the third gate opening,” in the combination required by the claim.
Claims 15-16 would be allowable based on their dependency on Claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rodder et al (US 2018/0166550) which discloses a finFET device with multiple vertical fins serving as conducting channel regions which limits gate length scaling [0003], and Ando et al (US 2018/0331096) which discloses finFET devices that have been formed with the channel extending outward from the substrate [0002].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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