DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Osawa et al. (US 2015/0055051) (hereafter Osawa).
Regarding claim 1, Fig. 15 of Osawa discloses an electronic device, comprising:
a substrate 24 (Fig. 15, paragraph 0029) having a surface (top horizontal surface of 24 in Fig. 15);
a first semiconductor 204 (Fig. 15, paragraph 0054) disposed on the surface of the substrate 24 (Fig. 15) and comprising a silicon semiconductor (“polysilicon layer” in paragraph 0054);
a first gate electrode 218 (Fig. 15, paragraph 0054) overlapping the first semiconductor 204 (Fig. 15) in view of a normal direction (vertical direction in Fig. 15) of the surface (top horizontal surface of 24 in Fig. 15);
a second semiconductor 224 (Fig. 15, paragraph 0054) disposed on the surface of the substrate 24 (Fig. 15) and comprising an oxide semiconductor (“IGZO” in paragraph 0054);
a second gate electrode 228 (Fig. 15, paragraph 0054) overlapping the second semiconductor 224 (Fig. 15) in view of the normal direction (vertical direction in Fig. 15) of the surface (top horizontal surface of 24 in Fig. 15); and
an electrode 230 (Fig. 15, paragraph 0055) disposed above and electrically connected to the second semiconductor 224 (Fig. 15), wherein the electrode 230 (Fig. 15) overlaps the second semiconductor 224 (Fig. 15) in view of the normal direction (vertical direction in Fig. 15) of the surface (top horizontal surface of 24 in Fig. 15).
Regarding claim 3, Fig. 15 of Osawa further discloses the electronic device as claimed in claim 1, wherein the second semiconductor 224 (Fig. 15) is disposed between the substrate 24 (Fig. 15) and the second gate electrode 228 (Fig. 15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Osawa as applied to claim 1 above, and further in view of Yamazaki et al. (US 2017/0025548) (hereafter Yamazaki548).
Regarding claim 2, Fig. 15 of Osawa discloses the electronic device as claimed in claim 1, however Fig. 15 of Osawa does not disclose the first gate electrode is disposed between the substrate and the first semiconductor.
Yamazaki548 discloses the first gate electrode 310 (Fig. 5, paragraph 0105) is disposed between the substrate 400 (Fig. 5, paragraph 0190) and the first semiconductor 406b (Fig. 5, paragraph 0223).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form the first gate electrode is disposed between the substrate and the first semiconductor, as taught by Yamazaki548, since the conductor 310 (Yamazaki548, Fig. 5, paragraph 0106) can be a multilayer film including a conductor that has a function of inhibiting penetration of oxygen.
Claims 4-10 are rejected under 35 U.S.C. 103 as being unpatentable over Osawa as applied to claims 3 and 1 above, and further in view of Yamazaki et al. (US 2016/0284862) (hereafter Yamazaki862).
Regarding claim 4, Fig. 15 of Osawa discloses the electronic device as claimed in claim 3, however Fig. 15 of Osawa does not disclose a third gate electrode overlapping the second semiconductor in view of the normal direction of the surface, wherein the third gate electrode is disposed between the second semiconductor and the substrate.
Yamazaki862 discloses a third gate electrode 165 (Fig. 12B, paragraph 0304) overlapping the second semiconductor 122 (Fig. 12B, paragraph 0102) in view of the normal direction (vertical direction in Fig. 12B) of the surface (top surface of 100 in Fig. 12B), wherein the third gate electrode 165 (Fig. 12B) is disposed between the second semiconductor 122 (Fig. 12B) and the substrate 100 (Fig. 12B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form a third gate electrode overlapping the second semiconductor in view of the normal direction of the surface, wherein the third gate electrode is disposed between the second semiconductor and the substrate, as taught by Yamazaki862, since the third gate electrode/conductive layer 165 (Yamazaki862, Fig. 12B, paragraph 0304) serves as a bottom gate and can supply the same potential or a different potential by being electrically connected to the gate electrode layer 160 (Yamazaki862, Fig. 12B, paragraph 0304).
Regarding claim 5, Fig. 15 of Osawa discloses the electronic device as claimed in claim 1, however Fig. 15 of Osawa does not disclose a third gate electrode overlapping the second semiconductor in view of the normal direction of the surface, wherein: the third gate electrode is disposed between the second semiconductor and the substrate, a first distance between the first gate electrode and the surface of the substrate is different from a second distance between the third gate electrode and the surface of the substrate.
Yamazaki862 discloses a third gate electrode (element number is not shown in Fig. 22A but see 165 in Fig. 12B, paragraph 0304) overlapping the second semiconductor (oxide semiconductor of 2100 in Fig. 22A; and see 122 in Fig. 12B) in view of the normal direction (vertical direction in Fig. 22A) of the surface (top surface of bottom layer in Fig. 22A), wherein: the third gate electrode (bottom gate of 2100 in Fig. 22A; and see 165 in Fig. 12B) is disposed between the second semiconductor (oxide semiconductor of 2100 in Fig. 22A; and see 122 in Fig. 12B) and the substrate (bottom layer of Fig. 22A), a first distance (distance between gate electrode of 2200 and bottom layer in Fig. 22A) between the first gate electrode (gate electrode of 2200 in Fig. 22A) and the surface of the substrate (bottom layer in Fig. 22A) is different from a second distance (distance between bottom gate of 2100 and top surface of bottom layer in Fig. 22A) between the third gate electrode (bottom gate of 2100 in Fig. 22A; and see 165 in Fig. 12B) and the surface of the substrate (bottom layer in Fig. 22A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form a third gate electrode overlapping the second semiconductor in view of the normal direction of the surface, wherein: the third gate electrode is disposed between the second semiconductor and the substrate, a first distance between the first gate electrode and the surface of the substrate is different from a second distance between the third gate electrode and the surface of the substrate, as taught by Yamazaki862, since the stack (Yamazaki862, paragraph 0364) of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated.
Regarding claim 6, Fig. 15 of Osawa in view of Yamazaki862 discloses the electronic device as claimed in claim 5, however Fig. 15 of Osawa does not disclose the first distance is less than the second distance.
Yamazaki862 discloses the first distance (distance between gate electrode of 2200 and bottom layer in Fig. 22A) is less than the second distance (distance between bottom gate of 2100 and top surface of bottom layer in Fig. 22A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form the first distance is less than the second distance, as taught by Yamazaki862, since the stack (Yamazaki862, paragraph 0364) of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated.
Regarding claim 7, Fig. 15 of Osawa discloses the electronic device as claimed in claim 1, however Fig. 15 of Osawa does not disclose a third distance between the first semiconductor and the surface of the substrate is less than a fourth distance between the second semiconductor and the surface of the substrate.
Yamazaki862 discloses a third distance (distance between vertical portion of bottom layer and horizontal portion of bottom layer in Fig. 22A) between the first semiconductor (vertical portion of bottom layer in Fig. 22A) and the surface of the substrate (horizontal portion of bottom layer in Fig. 22A) is less than a fourth distance (distance between oxide semiconductor of 2100 and horizontal portion of bottom layer in Fig. 22A) between the second semiconductor (oxide semiconductor of 2100 in Fig. 22A; and see 122 in Fig. 12B) and the surface of the substrate (horizontal portion of bottom layer in Fig. 22A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form a third distance between the first semiconductor and the surface of the substrate is less than a fourth distance between the second semiconductor and the surface of the substrate, as taught by Yamazaki862, since the stack (Yamazaki862, paragraph 0364) of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated.
Regarding claim 8, Fig. 15 of Osawa in view of Yamazaki862 discloses the electronic device as claimed in claim 7, however Fig. 15 of Osawa does not disclose a third gate electrode overlapping the second semiconductor in view of the normal direction of the surface, wherein: the third gate electrode is disposed between the second semiconductor and the substrate, a first distance between the first gate electrode and the surface of the substrate is different from a second distance between the third gate electrode and the surface of the substrate.
Yamazaki862 discloses a third gate electrode (bottom gate of 2100 in Fig. 22A; and see 165 in Fig. 12B, paragraph 0304) overlapping the second semiconductor (oxide semiconductor of 2100 in Fig. 22A; and see 122 in Fig. 12B) in view of the normal direction (vertical direction in Fig. 22A) of the surface (top surface of bottom layer in Fig. 22A), wherein: the third gate electrode (bottom gate of 2100 in Fig. 22A; and see 165 in Fig. 12B) is disposed between the second semiconductor (oxide semiconductor of 2100 in Fig. 22A; and see 122 in Fig. 12B) and the substrate (horizontal portion of bottom layer in Fig. 22A), a first distance (distance between gate electrode of 2200 and horizontal portion of bottom layer in Fig. 22A) between the first gate electrode (gate electrode of 2200 in Fig. 22A) and the surface of the substrate (horizontal portion of bottom layer in Fig. 22A) is different from a second distance (distance between bottom gate of 2100 and horizontal portion of bottom layer in Fig. 22A) between the third gate electrode (bottom gate of 2100 in Fig. 22A; and see 165 in Fig. 12B) and the surface of the substrate (horizontal portion of bottom layer in Fig. 22A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form a third gate electrode overlapping the second semiconductor in view of the normal direction of the surface, wherein: the third gate electrode is disposed between the second semiconductor and the substrate, a first distance between the first gate electrode and the surface of the substrate is different from a second distance between the third gate electrode and the surface of the substrate, as taught by Yamazaki862, since the stack (Yamazaki862, paragraph 0364) of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated.
Regarding claim 9, Fig. 15 of Osawa in view of Yamazaki862 discloses the electronic device as claimed in claim 8, however Fig. 15 of Osawa does not disclose the first distance is less than the second distance.
Yamazaki862 discloses the first distance (distance between gate electrode of 2200 and horizontal portion of bottom layer in Fig. 22A) is less than the second distance (distance between bottom gate of 2100 and horizontal portion of bottom layer in Fig. 22A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form the first distance is less than the second distance, as taught by Yamazaki862, since the stack (Yamazaki862, paragraph 0364) of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated.
Regarding claim 10, Fig. 15 of Osawa in view of Yamazaki862 discloses the electronic device as claimed in claim 8, however Fig. 15 of Osawa does not disclose the third gate electrode is disposed between the substrate and the second semiconductor.
Yamazaki862 discloses the third gate electrode (bottom gate of 2100 in Fig. 22A; and see 165 in Fig. 12B, paragraph 0304) is disposed between the substrate (horizontal portion of bottom layer in Fig. 22A) and the second semiconductor (oxide semiconductor of 2100 in Fig. 22A; and see 122 in Fig. 12B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form the third gate electrode is disposed between the substrate and the second semiconductor, as taught by Yamazaki862, since the third gate electrode/conductive layer 165 (Yamazaki862, Fig. 12B, paragraph 0304) serves as a bottom gate and can supply the same potential or a different potential by being electrically connected to the gate electrode layer 160 (Yamazaki862, Fig. 12B, paragraph 0304).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Osawa in view of Yamazaki862 as applied to claim 7 above, and further in view of Yamazaki et al. (US 2017/0025548) (hereafter Yamazaki548).
Regarding claim 11, Fig. 15 of Osawa in view of Yamazaki862 discloses the electronic device as claimed in claim 7, however Fig. 15 of Osawa and Yamazaki862 do not disclose the first gate electrode is disposed between the substrate and the first semiconductor.
Yamazaki548 discloses the first gate electrode 310 (Fig. 5, paragraph 0105) is disposed between the substrate 400 (Fig. 5, paragraph 0190) and the first semiconductor 406b (Fig. 5, paragraph 0223).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa in view of Yamazaki862 to form the first gate electrode is disposed between the substrate and the first semiconductor, as taught by Yamazaki548, since the conductor 310 (Yamazaki548, Fig. 5, paragraph 0106) can be a multilayer film including a conductor that has a function of inhibiting penetration of oxygen.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Osawa as applied to claim 1 above, and further in view of Shionoiri et al. (US 2014/0266305) (hereafter Shionoiri).
Regarding claim 12, Fig. 15 of Osawa discloses the electronic device as claimed in claim 1, however Fig. 15 of Osawa does not disclose a width of the second gate electrode is greater than a width of the first gate electrode.
Shionoiri discloses a width (see paragraph 0122, wherein “from 0.8 .mu.m to 1.5 .mu.m, inclusive”) of the second gate electrode 434 (Figs. 12 and 13B, paragraph 0114) is greater than a width (see paragraph 0121, wherein “from 0.35 .mu.m to 0.95 .mu.m, inclusive”) of the first gate electrode 404 (Figs. 12 and 13A, paragraph 0109).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa to form a width of the second gate electrode is greater than a width of the first gate electrode, as taught by Shionoiri, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 13, Fig. 15 of Osawa in view of Shionoiri discloses the electronic device as claimed in claim 12, however Fig. 15 of Osawa and Shionoiri do not disclose a first blocking element disposed between the first semiconductor and the surface of the substrate; a second blocking element disposed between the second semiconductor and the surface of the substrate, wherein the first blocking element is spaced apart from the second blocking element.
Fig. 18 of Osawa discloses a first blocking element (portion of 522 within 58 in Fig. 18, paragraph 0080) disposed between the first semiconductor 62 (Fig. 18, paragraph 0082) and the surface of the substrate 24 (Fig. 18); a second blocking element (portion of 522 within 60 in Fig. 18, paragraph 0080) disposed between the second semiconductor 128 (Fig. 18, paragraph 0085) and the surface of the substrate 24 (Fig. 18), wherein the first blocking element (portion of 522 within 58 in Fig. 18) is spaced (see Fig. 18, wherein portion of 522 between 58 and 60) part from the second blocking element (portion of 522 within 60 in Fig. 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa in view of Shionoiri to form a first blocking element disposed between the first semiconductor and the surface of the substrate; a second blocking element disposed between the second semiconductor and the surface of the substrate, wherein the first blocking element is spaced apart from the second blocking element, as taught by Fig. 18 of Osawa, since blocking elements/functional layer 522 (Osawa, Fig. 18, paragraph 0080) may be a stress relief layer, a light-blocking layer, a layer used in forming components such as capacitors.
Regarding claim 14, Fig. 15 of Osawa in view of Shionoiri and Fig. 18 of Osawa discloses the electronic device as claimed in claim 13, however Fig. 15 of Osawa and Shionoiri do not disclose a width of the second blocking element is greater than a width of the first blocking element.
Fig. 18 of Osawa discloses a width of the second blocking element (portion of 522 within 60 in Fig. 18, paragraph 0080) is greater than a width of the first blocking element (portion of 522 within 58 in Fig. 18, paragraph 0080).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fig. 15 of Osawa in view of Shionoiri to form a width of the second blocking element is greater than a width of the first blocking element, as taught by Fig. 18 of Osawa, since blocking elements/functional layer 522 (Osawa, Fig. 18, paragraph 0080) may be a stress relief layer, a light-blocking layer, a layer used in forming components such as capacitors.
Regarding claim 15, Fig. 15 of Osawa further discloses the electronic device as claimed in claim 12, further comprising (see paragraph 0073, wherein “Semiconducting oxide thin-film transistor structures 240 may be used in peripheral circuits such as display driver circuitry 18 and demultiplexer circuitry 20 and/or may be used in forming circuits for display pixels 22 in a liquid crystal display.”; and see Fig. 1, wherein multiple pixel circuit 22 are formed such that another 240 are formed in another pixel circuit 22 similar to Fig. 15):
a third semiconductor (another 224 (Fig. 15) in another pixel circuit 22 (Fig. 1), paragraph 0075) disposed on the surface of the substrate 24 (Fig. 15) and comprising an oxide semiconductor (“IGZO” in paragraph 0075); and
a fourth gate electrode (another 228 (Fig. 15) in another pixel circuit 22 (Fig. 1), paragraph 0075) overlapping the third semiconductor (another 224 (Fig. 15) in another pixel circuit 22 (Fig. 1)) in view of the normal direction (vertical direction in Fig. 15) of the surface (top surface of 24 in Fig. 15);
wherein the third semiconductor (another 224 (Fig. 15) in another pixel circuit 22 (Fig. 1)) is disposed between the substrate 24 (Fig. 15) and the fourth gate electrode (another 228 (Fig. 15) in another pixel circuit 22 (Fig. 1)).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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