Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claim 1 is objected to because of the following informalities: the “a width of second line portion” in line 17 should be “a width of the second line portion”.
Claim 11 is objected to because of the following informalities: the “a length of second pad portion” in line 17 should be “a length of the second pad portion”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claims 1, 14, 18, the limitation recites:
"a second bit line including a second line portion extending into the first extension region while crossing the memory cell array region in the first direction, a second connection portion extending from the first line portion in the first extension region..."
It is unclear how the second connection portion of the second bit line extends from the first line portion, which is recited as part of the first bit line. Therefore, the metes and bounds of the claim are unclear.
The specification appears to disclose that the second connection portion extends from the second line portion. For example, paragraph [0064] states:
"...a second connection portion CP2 extending from the second line portion LP2 in a direction away from the memory cell array region MCA..."
Accordingly, for purposes of examination, the examiner interprets the claims as intending to recite that the second connection portion extends from the second line portion, consistent with the disclosure.
However, the claims remain indefinite because the language presently recited is inconsistent with the disclosed structure.
Applicant is advised to amend the claims to clarify the relationship between the second connection portion and the second line portion as follows:
“a second connection portion extending from the [[first]] second line portion in the first extension region”.
Regarding claims 3-13, because of their dependency on claim 1, these claims are also objected for the reasons set forth above with respect to claim 1.
Regarding claims 15-17, because of their dependency on claim 14, these claims are also objected for the reasons set forth above with respect to claim 14.
Regarding claims 19-20, because of their dependency on claim 18, these claims are also objected for the reasons set forth above with respect to claim 18.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1. Seo et al. (US 20080203587) teaches semiconductor devices including bit lines extending through a memory cell array region and into adjacent extension regions, connection portions, and pad portions. Seo further teaches pad portions having widths greater than widths of corresponding line portions. See, e.g., Fig. 5 and paragraphs [0053], [0058]-[0059].
In addition, Fig. 5 of Seo appears to disclose a spacing relationship in which a distance between adjacent pad portions is smaller than a distance between adjacent conductive line portions. For example, Seo discloses a first distance SW1 and a third distance SW3, wherein SW3 is greater than SW1. See paragraph [0053].
However, the embodiment of Fig. 5 does not appear to disclose a third bit line disposed between the first and second bit lines and including a first end portion in the first extension region, as recited in claim 1.
Seo further discloses an alternative bit-line arrangement in Fig. 13B. While Fig. 13B appears to disclose a third bit line disposed between neighboring bit lines and including an end portion in an extension region, Seo does not expressly disclose or suggest in connection with the Fig. 13B embodiment the claimed spacing relationship requiring that:
"a minimum distance between the first pad portion and the second pad portion is less than a minimum distance between the first line portion and the third bit line."
Accordingly, the prior art of record does not teach or suggest the particular combination of (i) a third bit line disposed between the first and second bit lines and including a first end portion in the first extension region and (ii) the claimed relative spacing relationship between the pad portions and the bit lines. The Examiner has not identified any teaching or suggestion in the prior art of record that would have led one of ordinary skill in the art to combine these features in the manner recited in claim 1.
Therefore, claim 1, and claims depending therefrom, are allowable over the prior art of record.
Regarding claim 14. Seo et al. (US 20080203587) teaches a semiconductor device including bit lines extending through a memory cell array region and into adjacent extension regions, connection portions, pad portions, and conductive lines disposed between neighboring conductive lines. See, e.g., Figs. 5 and 13B. Seo further teaches bit line structures extending into extension regions adjacent to a memory cell array.
Lim et al. (US 20140021521) teaches an open bit line memory architecture including bit lines (BL), dummy bit lines (DBL), contacts 147, and metal lines 149 associated with dummy cells. See Fig. 2 and paragraphs [0040]-[0048].
However, the prior art of record, including Seo et al. and Lim et al., fails to teach or suggest the arrangement recited in claim 14 wherein a dummy contact plug is positioned relative to both an insulating pattern and an end portion of an intervening bit line. In particular, the prior art fails to teach or suggest:
"the dummy contact plugs include a first dummy contact plug, at least a portion of the first dummy contact plug is between the insulating pattern and the first end portion of the third bit line."
Although Lim teaches dummy bit lines and associated contact structures, neither Lim nor Seo discloses or suggests the claimed positional relationship among (i) the first dummy contact plug, (ii) the insulating pattern disposed between the first and second pad portions, and (iii) the first end portion of the third bit line. The Examiner has not identified any teaching or suggestion in the prior art of record that would have led one of ordinary skill in the art to provide the claimed arrangement.
Accordingly, claim 14, and claims depending therefrom, are allowable over the prior art of record.
Regarding claim 18. Seo et al. (US 20080203587) teaches semiconductor devices including bit lines extending through a memory cell array region and into adjacent extension regions, connection portions, pad portions, and insulating structures associated with bit line formations. Seo further teaches conductive lines disposed between neighboring conductive lines and bit line structures extending into extension regions. See, e.g., Figs. 5 and 13B.
Lim et al. (US 20140021521) teaches open bit line memory architectures including bit lines, dummy bit lines, contact structures, and associated insulating layers. See Fig. 2 and paragraphs [0040]-[0048].
However, the prior art of record, including Seo et al. and Lim et al., fails to teach or suggest the spacer arrangement recited in claim 18. In particular, the prior art fails to teach or suggest:
"an outer spacer including a first outer portion, a second outer portion, and a third outer portion, wherein the third outer portion covers a side surface of the insulating pattern toward the memory cell array region."
Although the cited references disclose bit line structures, insulating structures, and spacer structures, the cited references do not disclose or suggest the claimed positional relationship in which a third outer spacer portion covers a side surface of an insulating pattern facing the memory cell array region. The Examiner has not identified any teaching or suggestion in the prior art of record that would have led one of ordinary skill in the art to provide the claimed spacer configuration.
Accordingly, claim 18, and claims depending therefrom, are allowable over the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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