DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/7/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 19 is objected to because of the following informalities:
Claim 1 recites “the lower wiring is includes…” “is” should be omitted.
Appropriate correction is required.
Specification
The disclosure is objected to because of the following informalities:
Item “181” in Fig. 10 is not disclosed in spec.
Pg. 6, ¶ [0033], lines 3-4 reciting “each of the first and second upper insulating layers 32 and 52” should read “each of the first and second upper insulating layers 52 and 62.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-9, 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20230187212 A1) in view of Higihara (US 20030047812 A1)
Regarding claim 1, Hwang discloses (Fig. 3) A semiconductor device, comprising:
a substrate (101) including devices (112);
a lower insulating layer (153) on the substrate;
a lower wiring layer (M3) on the lower insulating layer and electrically connected to the devices;
a first upper insulating layer (163) on the lower insulating layer;
an upper contact (165) penetrating through the first upper insulating layer and connected to the lower wiring layer;
an upper wiring layer (166) on the first upper insulating layer and connected to the upper contact; and
a second upper insulating layer (164) on the first upper insulating layer and covering the upper wiring layer.
Hwang is silent regarding wherein the upper wiring layer includes an aluminum alloy, 0.01-3 wt% of the aluminum alloy is at least one dopant among Zn, Ni, V, and Cr, and a balance of the aluminum alloy includes Al.
Higihara discloses a conductive thin film aluminum alloy comprising a doped element from Cr in a content of 0.5 – 5 atom % is made to prevent the occurrence of hillocks (Higihara: ¶ [0013]). Artisans in the art would appreciate the doping amount of Cr in the alloy would protect the alloy from corrosion. As such, absent unpredictable result, a selected range of 0.01 -3 wt % of Cr would be achieved thru routine optimization. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the alloy layer taught be Higihara for the upper wiring layer of Hwang to achieve the corrosion protection.
Regarding claim 2, Hwang in view of Higihara discloses the semiconductor device of claim 1. Higihara further discloses (¶ [0013]) at least one dopant includes at least one of Zn and Ni (Zn) and at least one of V and Cr (Cr).
Regarding claim 3, Hwang in view of Higihara discloses the semiconductor device of claim 1 and the lower wiring layer (M3-155, 156) includes copper (Cu) (¶ [0028]), and wherein the upper contact (165) includes tungsten (W) (¶ [0029]).
Regarding claim 4, Hwang in view of Higihara discloses the semiconductor device of claim 1. Higihara further discloses at least one dopant includes 0.01-1 wt% of Zn (¶ [0013]).
Regarding claim 5, Hwang in view of Higihara discloses the semiconductor device of claim 1. Higihara further discloses at least one dopant includes 0.01-0.24 wt% of Ni (¶ [0013]).
Regarding claim 7, Hwang in view of Higihara discloses the semiconductor device of claim 1. Higihara further discloses at least one dopant includes 0.01-0.7 wt% Cr (¶ [0013]).
Regarding claim 8, Hwang in view of Higihara discloses the semiconductor device of claim 1. Though being silent regarding a conductive bonding layer between the upper wiring layer (166) and the first upper insulating layer (163), Hwang discloses the barrier layer between 163 and 165 (upper contact) and between. Artisans in the art would have appreciated a bonding layer would act as a diffusion barrier to stop interdiffusion of metals in direct contact. Though a barrier layer between 163 and 166 is not disclosed to avoid repetition, placing a barrier layer between 163 and 166 is predictable through routine optimization. As such, one of ordinary skill in the art before the effective filing date of the invention would have come placed a barrier layer to bond upper wiring layer and the first upper insulating layer to avoid interdiffusion between them.
Regarding claim 9, Hwang in view of Higihara discloses ([0028]) the semiconductor device of claim 8 and the conductive bonding layer (barrier layer) includes one of Ti, Ta, Ru, TiN, TiSiN, TiAlx, TaN, and WN.
Regarding claim 12, Hwang in view of Higihara discloses (Fig. 3) the device of claim 1, and the lower wiring layer (M3-155, 156) includes a wiring pattern (156) and a via (155) extending downwardly from the wiring pattern, and the lower insulating layer covers a lower surface of the wiring pattern and a side surface of the wiring pattern, and the via penetrates through a portion of the lower insulating layer, and the portion of the lower insulating layer is on the lower surface of the wiring pattern.
Regarding claim 13, Hwang in view of Higihara discloses (Fig. 3) the semiconductor device of claim 1, further comprising: a lower etch stop layer (150) on a lower surface of the lower insulating layer, wherein a via of the lower wiring layer penetrates through the lower etch stop layer.
Regarding claim 14, Hwang in view of Higihara discloses (Fig. 3) the semiconductor device of claim 13, further comprising: an upper etch stop layer (160) below the first upper insulating layer.
Regarding claim 15, Hwang in view of Higihara discloses (Fig. 3, ¶ [0051]) the semiconductor device of claim 1, further comprising a dielectric constant of the lower insulating layer (153) is lower than a dielectric constant of the first upper insulating layer (163).
Regarding claim 16, Hwang in view of Higihara discloses (Fig. 3) the semiconductor device of claim 1, further comprising an inclined surface of the lower wiring layer (M3) is inclined downwardly, an inclined surface of the upper contact (165) is inclined downwardly. Though not showing an inclined surface of the upper wiring layer being inclined upwardly, it is predictable to have the upper wiring layer lightly sloped sidewall as an alternative option. Thus, one of ordinary skill in the art before the effective filing date of the invention would have opted an upwardly inclined surface of the upper wiring layer for a diversity of applications.
Regarding claim 17, Hwang discloses (Fig. 3) A semiconductor device (Fig. 3), comprising:
a substrate (101) including a memory cell region (R1) and a peripheral circuit region (R2);
capacitors (MS, ¶ [0045]) on the memory cell region of the substrate; peripheral transistors (PS, ¶ [0047]) on the peripheral circuit region of the substrate;
an interlayer insulating layer (231) covering the capacitors and the peripheral transistors on the substrate;
lower contacts (135) in the interlayer insulating layer, the lower contacts electrically connected to the capacitors and the peripheral transistors;
a lower insulating layer (132, 143, 153) on the interlayer insulating layer;
a lower wiring layer (136, M2, M3) on the lower insulating layer and electrically connected to the lower contacts;
a first upper insulating layer (163) on the lower insulating layer;
an upper contact (165) penetrating through the first upper insulating layer and connected to the lower wiring layer;
an upper wiring layer (166) on the first upper insulating layer and connected to the upper contact; and
a second upper insulating layer (164) on the first upper insulating layer and covering the upper wiring layer.
Hwang is silent regarding wherein the upper wiring layer includes an aluminum alloy, 0.01-3 wt% of the aluminum alloy is at least one dopant among Zn, Ni, V, and Cr, and a balance of the aluminum alloy includes Al.
Higihara discloses a conductive thin film aluminum alloy comprising a doped element from Cr in a content of 0.5 – 5 atom % is made to prevent the occurrence of hillocks (Higihara: ¶ [0013]). Artisans in the art would appreciate the doping amount of Cr in the alloy would protect the alloy from corrosion. As such, absent unpredictable result, a selected range of 0.01 -3 wt % of Cr would be achieved thru routine optimization. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the alloy layer taught be Higihara for the upper wiring layer of Hwang to achieve the corrosion protection.
Regarding claim 18, Hwang in view of Higihara discloses the semiconductor device of claim 17. Higihara further discloses (¶ [0013]) at least one dopant includes at least one of Zn and Ni (Zn) and at least one of V and Cr (Cr).
Regarding claim 19, Hwang in view of Higihara discloses (Fig. 3) the semiconductor device of claim 17 and the lower insulating layer includes a plurality of lower insulating layers (132, 143, 153) stacked in order on the interlayer insulating layer, the lower wiring layer .
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20230187212 A1) in view of Higihara (US 20030047812 A1) and Nam (US 20200035602 A1)
Regarding claim 6. Hwang in view of Higidiscloses the semiconductor device of claim 1 but is silent regarding wherein the at least one dopant includes 0.01-0.6 wt% of V.
Nam discloses (¶ [0053]) a metal bonding layer comprising an Al alloy and Vanadium (V). Though Nam is silent to the weight percentage of Vanadium in the alloy, artisans in the art would have come up with the optimal range thru routine experimentation. Thus, one of ordinary skill in the art before the effective filing date of the invention would have come up with the content range of 0.01 – 0.6 wt% of element (V) in the Al alloy for optimal applications.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 20230187212 A1) in view of Higihara (US 20030047812 A1) and Drizlikh (US 7101787 B1)
Regarding claim 10, Hwang in view of Higihara discloses the semiconductor device of claim 1, but is silent to an anti-reflective layer on the upper wiring layer.
Drizlikh, an analogous art, discloses (col. 6, lines 12-22) applying an antireflective coating on a metal layer (col. 1, lines 56-59) to prevent fluorine contaminant compound that helps stabilize the resistance level of the metal layer.
Artisans in the art would have appreciated the practice of the coating a metal layer to prevent the precipitation of fluorine contaminants. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to employ the antireflective coating method of Drizlikh for the metal layer of Hwang to prevent contaminant precipitation on the metal layer, stabilizing metal resistance on the metal layer.
Regarding claim 11, Hwang in view of Higihara and Drizlikh discloses the semiconductor device of claim 10, wherein the anti-reflective layer includes TiN or TaN (col. 4, lines 6-11).
Regarding claim 20, Hwang (Fig. 3) discloses A semiconductor device (Fig. 3), comprising:
a substrate (101) including devices;
an interlayer insulating layer (231) covering the devices on the substrate;
a lower contact (135) on the interlayer insulating layer and connected to the devices;
a lower insulating layer (132, 143, 153) on the substrate;
a lower wiring layer (136, M2, M3) on the lower insulating layer and connected to the lower contact;
a first upper insulating layer (163) on the lower insulating layer;
an upper contact (165) penetrating through the first upper insulating layer and connected to the lower wiring layer;
a second upper insulating layer (164) on the first upper insulating layer; and an upper wiring layer (166) on the second upper insulating layer and connected to the upper contact.
Hwang is silent regarding wherein the upper wiring layer includes an aluminum alloy, 0.01-1.5 wt% of the aluminum alloy is at least one dopant among Zn and Ni, 0.01-1.5 wt% of the aluminum alloy is a second dopant among at least one of V and Cr, and a balance of the aluminum alloy includes Al.
Higihara discloses ¶ [0013]) a conductive thin film aluminum alloy comprising a doped element from Cr in a content of 0.5 – 5 atom % and another element from Zn in a content of 0.5 – 15 atom % to prevent the occurrence of hillocks. Artisans in the art would appreciate the doping amount of Cr and Zn in the alloy would protect the Al alloy from corrosion. As such, absent unpredictable result, a selected range of 0.01 -1.5 wt % of each Cr and Zn would be achieved thru routine optimization. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the alloy layer taught be Higihara for the upper wiring layer of Hwang to achieve the corrosion protection.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 20220344276 A1) and Hsu (US 20150145101 A1) discloses and an upper wiring layer on a DRAM cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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/DTH/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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