DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/9/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saha (10404188).
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With respect to claim 1, figs. 1- 2 of Saha (10404188) discloses a switch system, comprising: a hybrid switch comprising: an insulated-gate bipolar transistor (IGBT) (5); and a metal-oxide semiconductor field effect transistor (MOSFET) ((7); and a control circuit (30) comprising: an input terminal (terminal from 13) configured to receive a switch-off command; an IGBT drive (part of 40 driving the IGBT) circuit configured to switch off the IGBT (transferring the first switching control signal S1 via the first control signal line L1, the first switching element 5 is turned off.) in response to expiration of a first delay period (t5; After the first switching element 5 transitions to the off state, the second switching control signal S2 is brought into the ineffective state at time t6.) that begins in response to the switch-off command; and a MOSFET drive circuit (part of 40 driving the MOSFET) configured to: increase a gate-to-source voltage (Vds) of the MOSFET from a first voltage level (low) to a second voltage level (high) in response to the switch-off command (at time t4 prior to time t5 when the second switching element 7 starts the turn-off operation); drive the MOSFET at the second voltage level for a second delay period (t6) that begins in response to the switch-off command and that is longer than the first delay period (t5); and switch the MOSFET off in response to the expiration of the second delay period (t6) but fails to explicitly disclose a MOSFET drive circuit configured to: increase a gate-to-source voltage of the MOSFET from a first positive voltage level to a second positive voltage level to transition the MOSFET from a first MOSFET conductive state to a second MOSFET conductive state in response to the switch-off command wherein the MOSFET is more conductive in the second MOSFET conductive state than in the first MOSFET conductive state; drive the gate to source voltage of the MOSFET at the second positive voltage level for a second delay period that begins in response to the switch-off command and that is longer than the first delay period and decrease the gate-to- source voltage of the MOSFET to switch the MOSFET off in response to the expiration of the second delay period.
The MOSFET disclosed in Saha is disclosed as a switching element simply. If the MOSFET in figure 2. (column 4, lines 4-12) at the top is a PMOS switching element, it would have the ability to switch from a positive (at node connected to 81, i.e voltage at P – transistor) to positive (voltage at P) increase a gate-to-source voltage of the MOSFET from a first positive voltage level to a second positive voltage level to transition the MOSFET from a first MOSFET conductive state (minimally conducting when g-s is high) to a second MOSFET conductive state (conducting when g-s is low) in response to the switch-off command (g-s high) wherein the MOSFET is more conductive in the second MOSFET conductive state (g-s low) than in the first MOSFET conductive state; drive the gate to source voltage of the MOSFET at the second positive voltage level for a second delay period (second delay period would be obvious in propagation delay, Note Turn-on time is generally shorter than turn-off time in many devices because the transistor can be driven into saturation quickly, while turning off requires clearing stored charge in the base region. The difference depends on the device type, drive circuitry, and load conditions. For example, in BJTs, storage time is a major contributor to turn-off delay, whereas in MOSFETs, turn-off is often faster due to the absence of minority carrier storage). that begins in response to the switch-off command and that is longer than the first delay period and decrease the gate-to- source voltage of the MOSFET to switch the MOSFET off in response to the expiration of the second delay period (here obvious as the periods would run subsequentially in operating the motor).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to select a P-type device for the MOSFET switching elements of figure 2 as either type of PMOS or NMOS would be available and PMOS has the advantages of simpler manufacturing process.
With respect to claim 2, the circuit above produces switch system of claim 1, wherein the MOSFET comprises a silicon-carbide MOSFET (col. 7 lines 50-51).
With respect to claim 3, circuit above produces the switch system of claim 1, wherein the IGBT comprises a silicon IGBT (col. 7 lines 49-50).
With respect to claim 4, the circuit above produces the switch system of claim 1, but fails to disclose wherein the IGBT has a larger die area than the MOSFET. It is well known in the art to construct IGBT to have larger dies (generally in the order of 10. 5 x 10 mm) than MOSFETS (generally of order 7.35mm x 4.08mm). It would be obvious at the time the invention was made to a person having ordinary skill in the art to construct the IGBT and the MOSFET accordingly as they are readably accessible.
With respect to claim 5, the circuit above produces the switch system of claim 1, wherein: the input terminal (terminal 13) is further configured to receive a switch-on command (At time t3 subsequent to time t2 when the terminal-to-terminal voltage of the first switching element 5 (Vce) is substantially zero, the first switching control signal S1 is brought into the effective state. By transferring the first switching control signal S1 via the first control signal line L1, the first switching element 5 transitions from the off state to the on state (turn-on).); the MOSFET drive circuit is further configured to drive the gate-to-source voltage (Vds) of the MOSFET (7) at the first positive voltage level in response to the switch-on command; and the IGBT drive circuit is further configured to, in response to the switch-on command, drive a gate-to-emitter voltage (Vce) of the IGBT at a third voltage level that is greater than the first positive voltage level of the gate-to-source voltage of the MOSFET.
With respect to claim 6, circuit above produces the switch system of claim 1, wherein the control circuit further comprises: a first delay circuit (within the structure of the driver) configured to generate a first signal (S1) with a first delay corresponding to the first delay period (t5) in response to the switch-off command; and a second delay circuit (within the structure of the driver) configured to generate a second signal (S2) with a second delay corresponding to the second delay period (t6) in response to the switch-off command.
With respect to claim 7, the circuit above produces the switch system of claim 1, wherein the IGBT, the MOSFET, and the control circuit are co-packaged in a multi-chip integrated circuit package (power conversion device 1 is considered as such).
With respect to claim 8, the circuit above produces the switch system of claim 1, wherein the MOSFET drive circuit (40) further comprises a select terminal (control terminal at L21 or L22) and is configured to select one of two voltages (Vce or Vds high or low) at which to drive a gate of the MOSFET during an on-state of the MOSFET based on a select signal received at the select terminal during the on-state of the MOSFET.
With respect to claim 9, circuit above produces a hybrid switch system, comprising: a hybrid switch comprising: an insulated-gate bipolar transistor (IGBT) (5); and a metal-oxide semiconductor field effect transistor (MOSFET) (7); and a control circuit (30) comprising: an input terminal (terminal from 13) configured to receive a switch-off command; a delay generator (inside 40) configured to, in response to the switch-off command, generate an IGBT control signal having a first delay (t5; After the first switching element 5 transitions to the off state, the second switching control signal S2 is brought into the ineffective state at time t6.), and to generate a MOSFET control signal having a second delay (t6); an IGBT drive circuit configured to switch off the IGBT in response to the IGBT control signal having the first delay (transferring the first switching control signal S1 via the first control signal line L1, the first switching element 5 is turned off.); and a MOSFET drive circuit (MOSFET drive side within 40) configured to: increase a gate-to-source voltage (Vds) applied to the MOSFET from a first positive voltage (at node connected to 81) level to a second positive voltage level (node at P) to transition the MOSFET from a first MOSFET conductive state (high input off PMOS) to a second MOSFET conductive state (low input on PMOS) in response to the switch-off command (at time t4 prior to time t5 when the second switching element 7 starts the turn-off operation); wheriein the MOSFET is more conductive in the second MOSFET conductive state than in the first MOSFET conductive state, and to subsequently decrease the gate-to-source voltage to switch off the MOSFET in response to the MOSFET control signal having the second delay (t6).
With respect to claim 10, the circuit above produces the hybrid switch system of claim 9, wherein the MOSFET comprises a silicon-carbide MOSFET (col. 7 lines 50-51)..
With respect to claim 11, the circuit above produces the hybrid switch system of claim 9, wherein the IGBT comprises a silicon IGBT (col. 7 lines 49-50).
With respect to claim 12, the circuit above produces the hybrid switch system of claim 9, but fails to disclose wherein the IGBT has a larger die area than the MOSFET. It is well known in the art to construct IGBT to have larger dies (generally in the order of 10. 5 x 10 mm) than MOSFETS (generally of order 7.35mm x 4.08mm). It would be obvious at the time the invention was made to a person having ordinary skill in the art to construct the IGBT and the MOSFET accordingly as they are readably accessible.
With respect to claim 13, the circuit above produces the hybrid switch system of claim 9, wherein: the input terminal is further configured to receive a switch-on command (At time t3 subsequent to time t2 when the terminal-to-terminal voltage of the first switching element 5 (Vce) is substantially zero, the first switching control signal S1 is brought into the effective state. By transferring the first switching control signal S1 via the first control signal line L1, the first switching element 5 transitions from the off state to the on state (turn-on).); the MOSFET drive circuit is further configured to drive the gate-to-source voltage (Vds) of the MOSFET at the first positive voltage level in response to the switch-on command and at the second positive voltage level higher than the first positive voltage level in response to the switch-off command; and the IGBT drive circuit is further configured to drive a gate-to-emitter voltage (Vce) of the IGBT at a third voltage level in response to the switch-on command that is greater than the first voltage level of the gate-to-source voltage of the MOSFET.
With respect to claim 14, the circuit above produces the hybrid switch system of claim 9, wherein the MOSFET drive circuit (40) further comprises a select terminal (control terminal at L21 or L22) and is configured to select one of two voltages (Vce or Vds high or low) at which to drive a gate of the MOSFET during an on-state of the MOSFET based on a select signal received at the select terminal during the on-state of the MOSFET.
With respect to claim 15, the circuit above produces a method for controlling a hybrid switch (21 or 22), comprising: receiving a switch-on command for the hybrid switch ( At time t3 subsequent to time t2 when the terminal-to-terminal voltage of the first switching element 5 (Vce) is substantially zero, the first switching control signal S1 is brought into the effective state. By transferring the first switching control signal S1 via the first control signal line L1, the first switching element 5 transitions from the off state to the on state (turn-on).); driving an insulated-gate bipolar transistor (IGBT) of the hybrid switch in an IGBT conductive state with a first positive gate-to-source voltage in response to the switch-on command ; driving a metal-oxide semiconductor field effect transistor (MOSFET) of the hybrid switch in a first MOSFET conductive state in response to the switch-on command (when the pattern B is applied, the drive control section 20 causes the first switching element 5 to transition to the on state after causing the second switching element 7 to transition to the on state.); receiving a switch-off command for the hybrid switch; driving the MOSFET in a second MOSFET conductive state with a second positive gate-to source voltage that is higher than the first positive gate to source voltage in response to the switch-off command, wherein the MOSFET is more conductive in the second MOSFET conductive state than in the first MOSFET conductive state; driving the IGBT in an IGBT non-conductive state after a first delay period (t5), the first delay period beginning in response to the switch-off command (By transferring the second switching control signal S2 via the second control signal line L2, the second switching element 7 is turned off. As described above, when the pattern B is applied, the drive control section 20 causes the second switching element 7 to transition to the off state after causing the first switching element 5 to transition to the off state.); and driving the MOSFET in a MOSFET non-conductive state after a second delay period (t6), the second delay period beginning in response to the switch-off command and lasting longer than the first delay period.
With respect to claim 17, the circuit above produces the method for controlling a hybrid switch of claim 15, wherein: driving the MOSFET in the first MOSFET conductive state comprises applying a first gate-to-source voltage to the MOSFET (Vds); and driving the IGBT in the IGBT conductive state comprises applying a first gate-to-emitter voltage (Vce) to the IGBT greater than the first gate-to-source voltage applied to the MOSFET (in each switch section 2, a first control signal line L1 connecting a control terminal (gate terminal) of the first switching element 5 to the drive control section 20 and a second control signal line L2 connecting a control terminal (gate terminal) of the second switching element 7 to the drive control section 20 are provided independently of each other).( As the lines operate independent of each other, during a time when the IGBT is active and the MOSFET is inactive, the IGBT driving votlage is greater than the MOSFET driving voltage).
With respect to claim 18, the circuit above produces the method for controlling a hybrid switch of claim 15, wherein the IGBT is more conductive in the IGBT conductive state than the MOSFET in the first MOSFET conductive state. (Here, adjusting the conductivity of each switch is seen as being within the scope of the invention).
With respect to claim 19, the circuit above produces the method for controlling a hybrid switch of claim 15, further comprising: generating a first signal (S1) with a first delay corresponding to the first delay period (t5) in response to the switch-off command; and generating a second signal (S2) with a second delay (t6) corresponding to the second delay period in response to the switch-off command.
With respect to claim 20, the circuit above produces the method for controlling a hybrid switch of claim 19, further comprising selecting between the first MOSFET conductive state (On) and the second MOSFET conductive state (off) based at least in part on the switch-off command and the second signal.
Response to Arguments
Applicant's arguments filed 3/11/2026 have been fully considered but they are not persuasive.
With respect to applicant’s argument concerning claim 1, the Examiner points out that if a PMOS was used as provided by the obviousness rejection, the signals as such would read on the claimed subject matter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
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