DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Group 1 and Species 3 in the reply filed on 8/21/26 is acknowledged. The traversal is on the ground(s) that the species are not species. This is found persuasive and the species restriction is withdrawn.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2024/0038634, in view of Zhu, US 11,437,272.
Regarding claim 1, Kim (see marked up figure 1A below) teaches a semiconductor structure comprising:
a first area B having a transistor D2 with a backside source/drain contact 165A;
a metal level with at least one metal line 1;
a first set of vias 2 at a bottom of the metal level; and
a second set of vias 106A at a top of the metal line;
a second area C having a metal stub 3 in a region above a level of the transistor D2; and
a through dielectric via (TIV) 170/165C extending from a level below the transistor D2 to the metal stub 3.
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Kim fails to teach a top portion of the TIV is embedded in the metal stub.
Zhu (see marked up figure 8 below) teaches a top portion of the TIV 62 is embedded in the metal stub 1.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the embedded TIV of Zhu in the invention of Kim because an embedded TIV ensures a strong electrical connection by increasing the contacted surface area, and forms a strong mechanical bond because of the embedded portion. Though Zhu may be a different configuration, the concept of an embedded TIV is the only concept combined with Kim.
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With respect to claim 2, though Zhu fails to teach the metal stub has a first height H1 and the top portion of the TIV embedded in the metal stub has a second height H2, with H2 being 20% or more of H1, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative height through routine experimentation (MPEP 2144.05).
As to claim 3, though Kim and Zhu fail to teach the metal stub has a first horizontal width Wi and the TIV has a second horizontal width W2, with W2 being between about 60% and about 80% of W1, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative width through routine experimentation (MPEP 2144.05).
In re claim 4, though Kim fails to teach the metal stub has a first horizontal width W1, the at least one metal line has a width WO, and W1 is at least 10 times larger than WO, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative width through routine experimentation (MPEP 2144.05).
Concerning claim 5, though Kim fails to teach the metal stub has a first horizontal width W1, and W1 changes discontinuously along a sidewall of the metal stub, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative width through routine experimentation (MPEP 2144.05).
Pertaining to claim 6, Kim (see marked up figure 1A above) teaches a bottom surface of the metal stub 3 is substantially aligned with a bottom surface of the first set of vias 2.
In claim 7, Kim (see marked up figure 1A above) teaches a top surface of the metal stub 3 is substantially aligned with either a top surface of the one metal line 1 or a top surface of the second set of vias.
Regarding claim 8, wherein a bottom surface of the TIV 170/165C is substantially aligned with a bottom surface of the backside source/drain contact 165A of the transistor.
Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2024/0038634.
With respect to claim 16, Kim (see marked up figure 1A above) teaches a semiconductor structure comprising:
a first area B having a back-end-of-line (BEOL) region FSI, the BEOL region FSI including a first set of vias 2;
a metal level 1 with at least one metal line above the first set of vias 2; and
a second set of vias 160A above the metal level; and
a second area C having a metal stub 3,
wherein a bottom surface of the metal stub 3 is substantially aligned with a bottom surface of the first set of vias 2 and a top surface of the metal stub 3 is substantially aligned with either a top surface of the at least one metal line of the metal level 1 or a top surface of the second set of vias 160A,
Though Kim fails to teach the metal stub 3 has a first horizontal width that is at least 10 times larger than a width of the at least one metal line, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative width through routine experimentation (MPEP 2144.05).
As to claim 20, though Kim fails to teach sidewalls of the metal stub have discontinuous changes at locations, a level of the locations corresponds to either the top surface or a bottom surface of the at least one metal line of the metal level in the first area, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative width through routine experimentation (MPEP 2144.05).
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2024/0038634, as applied to claim 16 above, and further in view of Zhu, US 11,437,272.
As to claim 17, further comprising a through dielectric via (TIV) 170/165C.
Kim fails to teach the TIV has a top portion thereof embedded in the metal stub, wherein the metal stub has a first height and the top portion of the TIV embedded in the metal stub has a second height, and the second height is about 20% or more of the first height.
Zhu (see marked up figure 8 above) teaches a top portion of the TIV 62 is embedded in the metal stub 1.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the embedded TIV of Zhu in the invention of Kim because an embedded TIV ensures a strong electrical connection by increasing the contacted surface area, and forms a strong mechanical bond because of the embedded portion. Though Zhu may be a different configuration, the concept of an embedded TIV is the only concept combined with Kim.
Though Kim fails to teach the metal stub has a first height and the top portion of the TIV embedded in the metal stub has a second height, and the second height is about 20% or more of the first height, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative heights through routine experimentation (MPEP 2144.05).
In re claim 18, though Kim fails to teach the TIV has a second horizontal width that is about 60% to 80% of the first horizontal width of the metal stub, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative width through routine experimentation (MPEP 2144.05).
Concerning claim 19, Kim (see marked up figure 1A above) the first area B further comprises a transistor D2 and a backside source/drain contact 165B underneath the transistor D2, and wherein a bottom surface of the TIV 170/165C is substantially aligned with a bottom surface of the backside source/drain contact 165B underneath the transistor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach various aspects of the invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 9/2/26
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