DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Meunier et al. (U.S. Patent Application Publication Number 2021/0294363) and Summa et al. (U.S. Patent Application Publication Number 2024/0094751).
Regarding Claim 1, Meunier discloses a method for control loop sub-system voltage management, the method comprising:
detecting a requested dynamic clock voltage scaling (DCVS) (paragraphs 0034-0035; i.e., the dynamic voltage scaling [DVS] request can concurrently include a frequency [i.e., clock] change request) operating voltage as a final operating voltage (paragraph 0038; i.e., it is a “final” operating voltage for as long as the particular task that initiated the voltage change is running) and comparing the final operating voltage to a predetermined voltage range (paragraphs 0040 and 0042-0043; i.e., the DVS voltage change request is compared against the hardware coded clamps 176 and 177 [Figure 1] to ensure it falls within a required predetermined range);
setting the requested DCVS operating voltage when the final operating voltage is within the predetermined voltage range (paragraphs 0036 and 0052; i.e., if the requested DVS voltage is within the predetermined range, the voltage Vcore [Figure 1] is allowed to be changed); and
adjusting an output voltage (Figure 1, item Vcore) of a voltage regulator (Figure 1, item 115, paragraph 0036; i.e., a buck or linear regulator) through a voltage regulator feedback path (Figure 1, see connection between items 135, 130, 125, and 115) before receiving a power management integrated circuit acknowledgment (Figure 4, item 440, paragraph 0053; i.e., the interrupt pulse that is sent from the PMIC 110 to the SoC 140 is considered equivalent to the claimed “power management integrated circuit acknowledgment” because even though the DVS voltage change request is denied because it falls outside of the predetermined voltage range, it at least acknowledges to the SoC 140 that the DVS request was received by the PMIC 110; further, a first DVS voltage change request can be immediately accepted by the PMIC 110 without receiving any type of acknowledgement [see Figure 4, item 430]; but in a later DVS voltage change request, the PMIC 110 can reject the voltage change request with an acknowledgement because it is outside of the predetermined range by transmitting an interrupt to the SoC 140; thus, in the first case, the output voltage Vcore can be modified “before receiving a power management integrated circuit acknowledgment” [the interrupt 440]).
Meunier does not expressly disclose a current sink/source drive of a system-on-chip (SoC) that is set according to the requested DCVS operating voltage;
wherein the voltage regulator feedback path is between the voltage regulator and the current sink/source drive of the SoC; and
the output voltage is adjusted by modifying the current sink/source drive to change the output voltage through the voltage regulator feedback path.
In the same field of endeavor (e.g., voltage adjustment techniques), Summa teaches a current sink/source drive (Figure 2, item 252, paragraph 0029) of a system-on-chip (SoC) (Figure 2, item 202, paragraphs 0023 and 0035; i.e., the functionality of the test device 250, which includes the current sink/source drive 252, may be incorporated into the SoC 202) that is set according to a desired operating voltage (paragraph 0066; i.e., the controller 254 transmits a signal [paragraph 0033 - the desired operating voltage] that causes the current source 252 to output a particular control current ICTR [Figure 2], which has a known linear relationship with the internal supply voltage/operating voltage from voltage regulator 204.1);
wherein the voltage regulator feedback path is between the voltage regulator (Figure 2, item 204.1) and the current sink/source drive of the SoC (paragraphs 0023 and 0032-0033; i.e., the connections between items 204.1, 206, and 250 are equivalent to the claimed “voltage regulator feedback path”);
the output voltage is adjusted by modifying the current sink/source drive to change the output voltage through the voltage regulator feedback path (paragraphs 0023, 0032-0033, and 0066; i.e., the connections between items 204.1, 206, and 250 [“voltage regulator feedback path”] are used to sink or source a control current ICTR from the current source 252 in order adjust the output voltage of voltage regulator 204.1; the output voltage of the voltage regulator 204.1 is adjusted “through the voltage regulator feedback path” because that is the path that receives the control current ICTR).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Summa’s teachings of voltage adjustment techniques with the teachings of Meunier, for the purpose of allowing the SoC to directly control the output voltage, thereby allowing for fast voltage changes since some internal components of the PMIC can therefore be bypassed.
Regarding Claim 2, Summa discloses in which setting comprises drawing a sink current from the voltage regulator feedback path between the voltage regulator and the current sink/source drive of the SoC to increase the output voltage (paragraph 0047).
Regarding Claim 3, Summa discloses in which setting comprises driving a source current through the voltage regulator feedback path between the voltage regulator and the current sink/source drive of the SoC to decrease the output voltage (paragraph 0047).
Regarding Claim 4, Summa discloses in which adjusting the output voltage comprises controlling a feedback voltage on the voltage regulator feedback path (Figure 2, paragraphs 0024 and 0028; i.e., the resistor voltage divider R1 and R2 [Figure 3A] must be the component that ultimately provides the supply voltage to the IC sub-circuitry 210, which must occur via at least part of the equated “voltage regulator feedback path” since the resistor voltage divider R1 and R2 is the component that connects to multiplexer 206, which then connects to the IC sub-circuitry 210) to scale the output voltage (paragraphs 0023 and 0032-0033; i.e., the connections between items 204.1, 206, and 250 [“voltage regulator feedback path”] are used to sink or source a control current ICTR from the current source 252 in order adjust the voltage of voltage regulator 204.1).
Regarding Claim 5, Summa discloses in which controlling the feedback voltage comprises dynamically adjusting a resistor voltage divider on the voltage regulator feedback path (Figure 3A, items R1 and R2, paragraph 0041).
Regarding Claim 6, Summa discloses in which dynamically adjusting comprises driving a sink/source current to/from the resistor voltage divider to tune the output voltage (paragraphs 0023 and 0032-0033; i.e., the connections between items 204.1, 206, and 250 [“voltage regulator feedback path”] are used to sink or source a control current ICTR from the current source 252 in order adjust the voltage of voltage regulator 204.1).
Regarding Claim 7, Summa discloses in which the resistor voltage divider is integrated with the SoC (Figure 3A, items R1 and R2).
Regarding Claim 8, Summa discloses in which the resistor voltage divider is integrated with the voltage regulator (Figure 3A, items R1 and R2).
Regarding Claim 9, Summa discloses in which the current sink/source drive is controlled by sub-systems (SS) of the SoC (Figure 2, item 254, paragraphs 0033-0034; i.e., the functionality of the test device 250, which includes the controller 254 [the “sub-systems of the SoC”], may be incorporated into the SoC 202).
Regarding Claim 10, Summa discloses in which the current sink/source drive is controlled by a voltage regulator module of the SoC (Figure 2, item 254, paragraphs 0033-0034; i.e., the functionality of the test device 250, which includes the controller 254 [the “voltage regulator module of the SoC”], may be incorporated into the SoC 202).
Regarding Claim 11, Meunier discloses a control loop sub-system voltage management system comprising:
a system-on-chip (SoC) (Figure 1, item 140) operable according to a requested dynamic clock voltage scaling (DCVS) (paragraphs 0034-0035; i.e., the dynamic voltage scaling [DVS] request can concurrently include a frequency [i.e., clock] change request) operating voltage as a final operating voltage (paragraph 0038; i.e., it is a “final” operating voltage for as long as the particular task that initiated the voltage change is running) compared to a predetermined voltage range (paragraphs 0040 and 0042-0043; i.e., the DVS voltage change request is compared against the hardware coded clamps 176 and 177 [Figure 1] to ensure it falls within a required predetermined range), wherein when the final operating voltage is within the predetermined voltage range, modifying an output voltage (Figure 1, item Vcore) before receiving a power management integrated circuit acknowledgment (Figure 4, item 440, paragraph 0053; i.e., the interrupt pulse that is sent from the PMIC 110 to the SoC 140 is considered equivalent to the claimed “power management integrated circuit acknowledgment” because even though the DVS voltage change request is denied because it falls outside of the predetermined voltage range, it at least acknowledges to the SoC 140 that the DVS request was received by the PMIC 110; further, a first DVS voltage change request can be immediately accepted by the PMIC 110 without receiving any type of acknowledgement [see Figure 4, item 430]; but in a later DVS voltage change request, the PMIC 110 can reject the voltage change request with an acknowledgement because it is outside of the predetermined range by transmitting an interrupt to the SoC 140; thus, in the first case, the output voltage Vcore can be modified “before receiving a power management integrated circuit acknowledgment” [the interrupt 440]);
a voltage regulator (Figure 1, item 115, paragraph 0036; i.e., a buck or linear regulator); and
a voltage regulator feedback path (Figure 1, see connection between items 135, 130, 125, and 115).
Meunier does not expressly disclose the SoC comprising a current sink/source drive;
the current sink/source drive is operable to modify a current to change an output voltage;
wherein the voltage regulator feedback path is between the voltage regulator and the current sink/source drive of the SoC to adjust the output voltage of the voltage regulator by the current sink/source drive modifying the current through the voltage regulator feedback path.
In the same field of endeavor, Summa teaches the SoC (Figure 2, item 202) comprising a current sink/source drive (Figure 2, item 252, paragraphs 0023, 0029, and 0035; i.e., the functionality of the test device 250, which includes the current sink/source drive 252, may be incorporated into the SoC 202);
the current sink/source drive is operable to modify a current to change an output voltage (paragraph 0066; i.e., the controller 254 transmits a signal that causes the current source 252 to output a particular control current ICTR [Figure 2], which has a known linear relationship with the internal supply voltage/operating voltage from voltage regulator 204.1);
wherein the voltage regulator feedback path (paragraphs 0023 and 0032-0033; i.e., the connections between items 204.1, 206, and 250 are equivalent to the claimed “voltage regulator feedback path”) is between the voltage regulator (Figure 2, item 204.1) and the current sink/source drive of the SoC to adjust the output voltage of the voltage regulator by the current sink/source drive modifying the current through the voltage regulator feedback path (paragraphs 0023, 0032-0033, and 0066; i.e., the connections between items 204.1, 206, and 250 [“voltage regulator feedback path”] are used to sink or source a control current ICTR from the current source 252 in order adjust the output voltage of voltage regulator 204.1; the output voltage of the voltage regulator 204.1 is adjusted “through the voltage regulator feedback path” because that is the path that receives the control current ICTR).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 11.
Regarding Claim 12, Summa discloses in which the current sink/source drive is further operable to draw a sink current from the voltage regulator feedback path between the voltage regulator and the current sink/source drive of the SoC to increase the output voltage (paragraph 0047).
Regarding Claim 13, Summa discloses in which the current sink/source drive is further operable to drive a source current through the voltage regulator feedback path between the voltage regulator and the current sink/source drive of the SoC to decrease the output voltage (paragraph 0047).
Regarding Claim 14, Summa discloses a resistor voltage divider coupled between the voltage regulator feedback path and the output voltage (Figure 3A, items R1 and R2, paragraph 0041).
Regarding Claim 15, Summa discloses in which the resistor voltage divider is configured to control a feedback voltage on the voltage regulator feedback path (Figure 2, paragraphs 0024 and 0028; i.e., the resistor voltage divider R1 and R2 [Figure 3A] must be the component that ultimately provides the supply voltage to the IC sub-circuitry 210, which must occur via at least part of the equated “voltage regulator feedback path” since the resistor voltage divider R1 and R2 is the component that connects to multiplexer 206, which then connects to the IC sub-circuitry 210) and scale the output voltage (paragraphs 0023 and 0032-0033; i.e., the connections between items 204.1, 206, and 250 [“voltage regulator feedback path”] are used to sink or source a control current ICTR from the current source 252 in order adjust the voltage of voltage regulator 204.1).
Regarding Claim 16, Summa discloses in which the current sink/source drive is further operable to drive a sink/source current to/from the resistor voltage divider to tune the output voltage (paragraphs 0023 and 0032-0033; i.e., the connections between items 204.1, 206, and 250 [“voltage regulator feedback path”] are used to sink or source a control current ICTR from the current source 252 in order adjust the voltage of voltage regulator 204.1).
Regarding Claim 17, Summa discloses in which the resistor voltage divider is integrated with the SoC (Figure 3A, items R1 and R2).
Regarding Claim 18, Summa discloses in which the resistor voltage divider is integrated with the voltage regulator (Figure 3A, items R1 and R2).
Regarding Claim 19, Summa discloses in which the SoC further comprises sub-systems (SS) operable to control the current sink/source drive (Figure 2, item 254, paragraphs 0033-0034; i.e., the functionality of the test device 250, which includes the controller 254 [the “sub-systems of the SoC”], may be incorporated into the SoC 202).
Regarding Claim 20, Summa discloses in which the SoC further comprises a voltage regulator module operable to control the current sink/source drive (Figure 2, item 254, paragraphs 0033-0034; i.e., the functionality of the test device 250, which includes the controller 254 [the “voltage regulator module of the SoC”], may be incorporated into the SoC 202).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a method for controlling sub-system voltages in an SoC.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
Prosecution Insights