DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11, 12 and 14-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipoated by Idapalapati (US 2017/0269984).
As to claim 1, Idapalapati discloses a reconfigurable processor, comprising:
an array of configurable units configurable to execute an application instrumented with at least one progress milestone (¶0020);
a control bus coupled to configurable units in the array of configurable units (¶0026); and
a hang detection circuit coupled to the control bus and including a timer that resets in response to receiving a control signal via the control bus (¶0035-¶0036);
wherein a configurable unit in the array of configurable units sends the control signal, in response to completion of a progress milestone in the at least one progress milestone, to the hang detection circuit via the control bus (¶0033 & ¶0039-¶0041); and
the hang detection circuit detects a hang condition in the execution of the application based on an expiration of the timer (¶0042).
As to claim 2, Idapalapati discloses the reconfigurable processor of claim 1, the hang detection circuit further comprising: a second timer that resets in response to receiving a second control signal via the control bus that indicates completion of a second progress milestone in the at least one progress milestone; wherein the hang detection circuit also detects the hang condition based on an expiration of either the timer or the second timer (¶0042).
As to claim 3, Idapalapati discloses the reconfigurable processor of claim 1, the hang detection circuit further comprising: a second timer that resets in response to receiving a second control signal via the control bus that indicates completion of a second progress milestone in the at least one progress milestone; wherein the hang detection circuit detects the hang condition based on an expiration of both the timer and the second timer (¶0042).
As to claim 4, Idapalapati discloses the reconfigurable processor of claim 1, wherein the timer also resets in response to receiving a second control signal via the control bus that indicates completion of a second progress milestone in the at least one progress milestone (¶0048).
As to claim 5, Idapalapati discloses the reconfigurable processor of claim 1, the array of configurable units coupled to an interface unit that includes the hang detection circuit (Fig. 2).
As to claim 6, Idapalapati discloses the reconfigurable processor of claim 1, the hang detection circuit further comprising a force-quit controller that stops execution of the application on the array of configurable units in response to detecting the hang condition (¶0031-¶0032, interrupt terminates process).
As to claim 7, Idapalapati discloses the reconfigurable processor of claim 1, further comprising: an external interface circuit coupled to a host computer through an external communication link; an internal network coupled to the external interface circuit; and an internal interface circuit coupled to the internal network and the control bus, the internal interface circuit including the hang detection circuit; wherein the hang detection circuit further sends a hang message to the external interface circuit over the internal network in response to detecting the hang condition (¶0024, ¶0026 & ¶0035).
As to claim 8, Idapalapati discloses the reconfigurable processor of claim 7, the external interface circuit further including a network recovery circuit that receives the hang message and sends an interrupt to the host computer through the external communication link in response (¶0031).
As to claim 9, Idapalapati discloses the reconfigurable processor of claim 7, the internal interface circuit further including a force-quit controller, wherein the external interface circuit sends a force quit message to the force-quit controller over the internal network in response to receiving the hang message, wherein the force-quit controller stops execution of the application on the array of configurable units in response to receiving the hang message (¶0031-¶0032).
As to claim 11, Idapalapati discloses a method for detecting an application that has hung during execution in an array of configurable units having a control bus, the method comprising:
setting a timer in a hang detection circuit to a timeout value, the hang detection circuit coupled to the control bus (¶0064);
in response to encountering a progress milestone during execution of the application in the array of configurable units, sending a control signal via a control bus from a configurable unit in the array of configurable units to the hang detection circuit (¶0033 & ¶0039-¶0041);
resetting the timer in response to receiving the control signal via the control bus (¶0035-¶0036); and
in response to the timer expiring, detecting a hang condition (¶0042).
As to claim 12, Idapalapati discloses the method of claim 11, further comprising stopping execution of the application on the array of configurable units in response to detecting the hang condition (¶0031-¶0032, interrupt terminates process).
As to claim 14, Idapalapati discloses the method of claim 11, further comprising: determining a value for the timer based on an expected time between times that the progress milestone is to be encountered during execution of the application; and initiating the timer with the value (¶0043 & ¶0064).
As to claim 15, Idapalapati discloses the method of claim 11, further comprising: sending a hang message to an external interface circuit over an internal network coupling the array of configurable units to the external interface circuit in response to detecting the hang condition; and sending an interrupt from the external interface circuit to a host computer through an external communication link in response to receiving the hang message (¶0049 & ¶0081).
As to claim 16, Idapalapati discloses the method of claim 15, further comprising: sending a force quit message to a force-quit controller over the internal network in response to receiving the hang message; and stopping execution of the application on the array of configurable units in response to receiving the force quit message (¶0031-¶0032, interrupt terminates process).
As to claim 17, Idapalapati discloses a computing system comprising:
a host computer (¶0024); an external communication link (¶0026); a
coarse-grained reconfigurable architecture processor that includes (¶0027):
an external interface circuit coupled to the host computer through the external communication link (¶0024);
an internal network coupled to the external interface circuit (¶0034);
an array of configurable units configurable to execute an application instrumented with at least one progress milestone (¶0020);
a control bus coupled to configurable units in the array of configurable units (¶0026);
an internal interface circuit coupled to the internal network and the control bus, the internal interface circuit including hang detection circuit with a timer that resets in response to receiving a control signal via the control bus; wherein a configurable unit in the array of configurable units sends the control signal, in response to completion of a progress milestone of the at least one progress milestone, to the hang detection circuit via the control bus (¶0035-¶0036 & ¶0039-¶0041)); and
the hang detection circuit detects a hang condition in the execution of the application based on an expiration of the timer (¶0042).
As to claim 18, Idapalapati discloses the computing system of claim 17, wherein the hang detection circuit sends a hang message to the external interface circuit over the internal network in response to detecting the hang condition (¶0049 & ¶0081).
As to claim 19, Idapalapati discloses the computing system of claim 18, wherein the external interface circuit sends an interrupt to the host computer through the external communication link in response to receiving the hang message (¶0031).
As to claim 20, Idapalapati discloses the computing system of claim 18, the internal interface circuit further including a force-quit controller, wherein the external interface circuit sends a force quit message to the force-quit controller over the internal network in response to receiving the hang message, wherein the force-quit controller stops execution of the application on the array of configurable units in response to receiving the hang message.
Allowable Subject Matter
Claims 10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prior art Naderi (US 2008/0307148) discloses a system for bus communication includes a first port coupled to a bus, comprising a first engine configured to respond to bus signals on the bus, according to a predetermined protocol. A second port couples to the bus, comprising a second engine configured to respond to bus signals according to the predetermined protocol. A control module couples to the second port and is configured to receive a port state signal, and to disable the second port based on the received port state signal (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES EHNE whose telephone number is (571)272-2471. The examiner can normally be reached 8:00-5:00 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLES EHNE/ Primary Examiner, Art Unit 2113
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