DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Claim(s) 1-9 in the reply filed on 07/21/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202410423676.5, filed on 06/01/2024.
Information Disclosure Statement
No Information Disclosure Statement (IDS) has been filed on record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over John H. Zhang et al, (hereinafter ZHANG), US 9812365 B1, in view of Ruilong Xie et al, (hereinafter XIE), US 9412616 B1.
Regarding Claim 1, ZHANG teaches a method for manufacturing (Figs. 2A-2O, methods of cutting gate structures on transistor devices, [Col. 4, Lines 19-20]) a semiconductor device (Figs. 2A-2O, 100, product), comprising:
providing a semiconductor substrate (Figs. 2A-2O, 102), on which a plurality of gate structures (Figs. 2A-2O/Fig. 2B, 104, sacrificial gate structures) arranged at intervals and a first dielectric layer (Figs. 2A-2O/Fig. 2B, 110, insulating material) filling a gap between adjacent gate structures (Figs. 2A-2O/Fig. 2B, 104, sacrificial gate structures) are formed;
replacing a portion of the first dielectric layer (Figs. 2A-2O/Fig. 2C, 110, insulating material) away from the semiconductor substrate (Figs. 2A-2O/Fig. 2C, 102) with a second dielectric layer (Figs. 2A-2O/Fig. 2D, 112, insulating material);
forming a patterned third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) on the gate structure (Figs. 2A-2O/Fig. 2F, 104, sacrificial gate structures) and the second dielectric layer (Figs. 2A-2O/Fig. 2F, 112, insulating material), wherein the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) has an opening (Figs. 2A-2O/Fig. 2H, 118A, opening), and the opening (Figs. 2A-2O/Fig. 2H, 118A, opening) exposes a surface of a predetermined gate removal area of the gate structure (Figs. 2A-2O/Fig. 2I, 101C/101D, gates);
using the third dielectric layer as a mask (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) to selectively remove the gate structure (Figs. 2A-2O/Fig. 2J, [Col. 7, Lines 29-36]) exposed by the opening (Figs. 2A-2O/Fig. 2H, 118A, opening; Figs. 2A-2O/Fig. 2I, 104S, upper surface of the axial portions of the sacrificial gate structures, 104) to form a gate cutting groove (Figs. 2A-2O, 120, gate-cut cavities);
forming a fourth dielectric layer (Figs. 2A-2O/Fig. 2K, 124, insulating material) in the gate cutting groove (Figs. 2A-2O/Fig. 2K, 120, gate-cut cavities), wherein the fourth dielectric layer (Figs. 2A-2O/Fig. 2K, 124, insulating material) also covers the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask); and
removing the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) and a portion of the fourth dielectric layer (Figs. 2A-2O/Fig. 2L, 124, insulating material) that are higher than the gate structure (Figs. 2A-2O/Fig. 2L, 104, sacrificial gate structures) through a planarization process ([Col. 7, Lines 43-45]) to form a partially cut gate structure (Figs. 2A-2O, 124, insulating gate-cut structures).
Though ZHANG’s product (Fig. 2O, 100) as exhibited in Figure 20 does demonstrate the remaining of the third dielectric layer (Fig. 2O, 116, protective insulating material) in the final structure, ZHANG does not explicitly disclose a method for manufacturing a semiconductor device, comprising: removing the third dielectric layer and a portion of the fourth dielectric layer that are higher than the gate structure through a planarization process to form a partially cut gate structure.
XIE teaches a method for manufacturing (Figs. 2A-2T, methods for forming single and double diffusion breaks on IC products) a semiconductor device (Figs. 2A-2T, 100 product), comprising: removing the third dielectric layer (Figs. 2A-2T; From Fig. 2C, 122, silicon nitride material layer to Fig. 2I, to Fig. 2Q, where no presence of 122) and a portion of the fourth dielectric layer (Figs. 2A-2T; from Fig. 2F, 130, silicon nitride material layer to Fig. 2G) that are higher than the gate structure (Figs. 2A-2T; Fig. 2Q, 106, fins) through a planarization process ([Col. 11, Lines 5-15]) to form a partially cut gate structure (Figs. 2A-2T; Fig. 2J/Fig. 2Q, 160, DDB isolation structures).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG to incorporate the teachings of XIE such that a method for manufacturing a semiconductor device, comprising: removing the third dielectric layer and a portion of the fourth dielectric layer that are higher than the gate structure through a planarization process to form a partially cut gate structure, so that the doble diffusion breaks (DDB) isolation structures and the single diffusion breaks (SDB) isolation structures are therefore self-aligned with respect sidewall spacers formed adjacent the gate structures on the product (XIE, [Col. 12, Lines 55-65]).
Regarding Claim 2, ZHANG as modified by XIE teaches the method of manufacturing a semiconductor device according to claim 1.
ZHANG further teaches the method for manufacturing (Figs. 2A-2O, methods of cutting gate structures on transistor devices, [Col. 4, Lines 19-20]) the semiconductor device (Figs. 2A-2O, 100, product), wherein, replacing the portion of the first dielectric layer (Figs. 2A-2O/Fig. 2C, 110, insulating material) away from the semiconductor substrate (Figs. 2A-2O/Fig. 2C, 102) with the second dielectric layer includes (Figs. 2A-2O/Fig. 2D, 112, insulating material):
etching (Fig. 2C, recess etching process, [Col. 6, Lines 12-20]) the first dielectric layer (Figs. 2A-2O/Fig. 2C, 110, insulating material) to remove the portion of the first dielectric layer (Figs. 2A-2O/Fig. 2C, 110, insulating material) away from the semiconductor substrate (Figs. 2A-2O, 100, product) to form a trench (Fig. 2C, recess, [Col. 6, Lines 12-20]);
forming a second dielectric material layer (Figs. 2A-2O/Fig. 2D, 112, insulating material) in the trench (Fig. 2C, recess, [Col. 6, Lines 12-20]), wherein the second dielectric material layer (Figs. 2A-2O/Fig. 2D, 112, insulating material) fills the trench (Fig. 2C, recess, [Col. 6, Lines 12-20]) and covers the gate structures (Figs. 2A-2O/Fig. 2B, 104, sacrificial gate structures) on both sides of the trench (Fig. 2C, recess, [Col. 6, Lines 12-20]); and removing a portion ([Col. 6, 21-24]) of the second dielectric material layer (Figs. 2A-2O/Fig. 2D, 112, insulating material) higher than the gate structure (Figs. 2A-2O/Fig. 2B, 104, sacrificial gate structures) through a planarization process ([Col. 6, Lines 21-29]) to form the second dielectric layer (Figs. 2A-2O/Fig. 2D, 112, insulating material).
Regarding Claim 4, ZHANG as modified by XIE teaches the method of manufacturing a semiconductor device according to claim 1.
ZHANG further teaches the method for manufacturing (Figs. 2A-2O, methods of cutting gate structures on transistor devices, [Col. 4, Lines 19-20]) the semiconductor device (Figs. 2A-2O, 100, product), wherein, forming the patterned third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) on the gate structure (Figs. 2A-2O/Fig. 2F, 104, sacrificial gate structures) and the second dielectric layer (Figs. 2A-2O/Fig. 2F, 112, insulating material), includes:
forming a patterned sacrificial mask layer (Figs. 2A-2O/Figs. 2H, 118, patterned etch mask) on the gate structure (Figs. 2A-2O/Fig. 2F, 104, sacrificial gate structures) and the second dielectric layer (Figs. 2A-2O/Fig. 2D, 112, insulating material), wherein the sacrificial mask layer (Figs. 2A-2O/Figs. 2H, 118, patterned etch mask) covers the surface of the predetermined gate removal area (annotated Figure 2H) of the gate structure (Fig. 2H, 101C/101D, gates) and a surface of a portion (annotated Figure 2H) of the second dielectric layer (Figs. 2A-2O/Fig. 2H, 112, insulating material) on both sides (annotated Figure 2H) of the gate structure (Fig. 2H, 101C/101D, gates);
forming the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) on the gate structure (Figs. 2A-2O/Fig. 2F, 104, sacrificial gate structures) and a portion of the second dielectric layer (Figs. 2A-2O/Fig. 2F, 112, insulating material) that are not covered (annotated Figure 2H) by the sacrificial mask layer (Figs. 2A-2O/Figs. 2H, 118, patterned etch mask); and
selectively removing (annotated Figure 2H) the sacrificial mask layer (Figs. 2A-2O/Figs. 2H, 118, patterned etch mask) to form the opening (Figs. 2A-2O/Fig. 2H, 118A, opening) in the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask).
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Regarding Claim 5, ZHANG as modified by XIE teaches the method of manufacturing a semiconductor device according to claim 4.
ZHANG further teaches the method for manufacturing (Figs. 2A-2O, methods of cutting gate structures on transistor devices, [Col. 4, Lines 19-20]) the semiconductor device (Figs. 2A-2O, 100, product), wherein, forming the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) on the gate structure (Figs. 2A-2O/Figs. 2F/2H, 104, sacrificial gate structures) and the portion of the second dielectric layer (Figs. 2A-2O/Fig. 2F, 112, insulating material) that are not covered by the sacrificial mask layer (Figs. 2A-2O/Figs. 2F-2H, 118, patterned etch mask) includes:
forming a third dielectric material layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask), wherein the third dielectric material layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) covers the sacrificial mask layer (Figs. 2A-2O/Figs. 2F-2H, 118, patterned etch mask) and covers a surface of the gate structure (Figs. 2A-2O/Figs. 2F/2H, 104, sacrificial gate structures) and a surface of the portion of the second dielectric layer (Figs. 2A-2O/Fig. 2F, 112, insulating material) that are exposed by the sacrificial mask layer (Figs. 2A-2O/Figs. 2F-2H, 118, patterned etch mask); and
removing a portion of the third dielectric material layer higher than the sacrificial mask layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) through a planarization process ([Col. 6, Lines 50-60]) to form the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116, protective insulating material).
Regarding Claim 6, ZHANG as modified by XIE teaches the method of manufacturing a semiconductor device according to claim 4.
ZHANG further teaches the method for manufacturing (Figs. 2A-2O, methods of cutting gate structures on transistor devices, [Col. 4, Lines 19-20]) the semiconductor device (Figs. 2A-2O, 100, product), wherein, a sidewall structure (Fig. 2H, 105, sidewall spacer) is further formed on a sidewall (annotated Figure 2H) of the gate structure (Fig. 2H, 104, sacrificial gate structure), the gate structure (Fig. 2H, 104, sacrificial gate structure) includes a gate sacrificial layer (annotated Figure 2H) and a gate mask layer (Fig. 2H, 106A, selectively etchable layer) formed on the gate sacrificial layer (annotated Figure 2H), and the opening (Figs. 2A-2O/Fig. 2H, 118A, opening; Figs. 2A-2O/Fig. 2I, 104S, upper surface of the axial portions of the sacrificial gate structures, 104) exposes the surface of the predetermined gate removal area (annotated Figure 2H, 101C/101D, gates) of the gate structure (Fig. 2H, 104, sacrificial gate structure) and a surface of the sidewall structure (Fig. 2H, 105, sidewall spacer) on both sides of the gate structure (Fig. 2H, 104, sacrificial gate structure).
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Regarding Claim 8, ZHANG as modified by XIE teaches the method of manufacturing a semiconductor device according to claim 6.
ZHANG further teaches the method for manufacturing (Figs. 2A-2O, methods of cutting gate structures on transistor devices, [Col. 4, Lines 19-20]) the semiconductor device (Figs. 2A-2O, 100, product), wherein, in a step of replacing the portion of the first dielectric layer (Figs. 2A-2O/Fig. 2D, 110, insulating material) away from the semiconductor substrate (Figs. 2A-2O/Fig. 2D, 102) with a second dielectric layer (Figs. 2A-2O/Fig. 2D, 112, insulating material), a bottom surface (annotated Figure 2D) of the second dielectric layer (Figs. 2A-2O/Fig. 2D, 112, insulating material) is lower than a top surface (annotated Figure 2D) of the gate sacrificial layer (Figs. 2A-2O/Fig. 2D, 104, sacrificial gate structures).
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Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of XIE as applied to claim(s) 1-2, 4-6, and 8 above and further in view of Nan Wang, (hereinafter WANG), US 20220028990 A1, and Poren Tang, (hereinafter TANG), US 20210384079 A1.
Regarding Claim 3, ZHANG as modified by XIE teaches the method of manufacturing a semiconductor device according to claim 1.
ZHANG further teaches the method for manufacturing (Figs. 2A-2O, methods of cutting gate structures on transistor devices, [Col. 4, Lines 19-20]) the semiconductor device (Figs. 2A-2O, 100, product), wherein, each of the second dielectric layer (Figs. 2A-2O/Fig. 2D, 112, insulating material), the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask), and the fourth dielectric layer (Figs. 2A-2O/Fig. 2L, 124, insulating material) includes a high- density plasma dielectric layer (HDP layer of silicon dioxide, [Col. 6, Lines 21-25]).
ZANG as modified by XIE does not explicitly disclose the method of manufacturing a semiconductor device, wherein, the first dielectric layer includes a flowable dielectric layer.
WANG teaches the method of manufacturing a semiconductor device (Figs. 1-5, method for forming a semiconductor structure, [0028]), wherein, the first dielectric layer (Fig. 6, 102, first mask layer is a dielectric material, [0061-0062]) includes a flowable dielectric layer (the dielectric material layer is formed using a flowable chemical vapor deposition (FCVD) process, [0110]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHANG as modified by XIE to incorporate the teachings of WANG such that the method of manufacturing a semiconductor device, wherein, the first dielectric layer includes a flowable dielectric layer, so that the flowable chemical vapor deposition process of forming the dielectric material layer, has good filling capability, is suitable for filling in opening of a high aspect ratio, is advantageous for reducing the probability that defects such as empty holes are formed in the dielectric material layer, and is correspondingly advantageous for improving the film formation quality of the dielectric layer (WANG, [0110]).
Though ZHANG teaches the method of manufacturing a semiconductor device, wherein, the second dielectric layer includes a high-density plasma (HDP) dielectric layer, ZHANG as modified by XIE and WANG does not explicitly disclose the method of manufacturing a semiconductor device, wherein, each of the second dielectric layer, the third dielectric layer, and the fourth dielectric layer includes a high-density plasma dielectric layer.
TANG teaches the method of manufacturing a semiconductor device (a method for fabricating a semiconductor device, [0006]), wherein, each of the second dielectric layer, the third dielectric layer, and the fourth dielectric layer (Figs. 8/10/13, 250/270/290, protective layer is made of silicon oxide/first dielectric layer/second dielectric layer, [0041]) includes a high-density plasma dielectric layer (the initial protective material layer may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process, [0040-0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHANG as modified by XIE and WANG to incorporate the teachings of TANG such that the method of manufacturing a semiconductor device, wherein, each of the second dielectric layer, the third dielectric layer, and the fourth dielectric layer includes a high-density plasma dielectric layer, so that the arrangement improve the performance of MOS transistors (TANG, [0005]).
Claim(s) 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of XIE as applied to claim(s) 1-2, 4-6, and 8 above and further in view of TANG as applied to claim(s) 3 above.
Regarding Claim 7, ZHANG as modified by XIE teaches the method of manufacturing a semiconductor device according to claim 6.
ZHANG further teaches the method for manufacturing (Figs. 2A-2O, methods of cutting gate structures on transistor devices, [Col. 4, Lines 19-20]) the semiconductor device (Figs. 2A-2O, 100, product), wherein, using the third dielectric layer as the mask (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) to selectively remove the gate structure (Figs. 2A-2O/Fig. 2J, [Col. 7, Lines 29-36]) exposed by the opening (Figs. 2A-2O/Fig. 2H, 118A, opening; Figs. 2A-2O/Fig. 2I, 104S, upper surface of the axial portions of the sacrificial gate structures, 104) to form a gate cutting groove (Figs. 2A-2O, 120, gate-cut cavities)includes:
using the third dielectric layer (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) as a mask to selectively remove the gate mask layer (Figs. 2A-2O/Fig. 2J, [Col. 7, Lines 29-36]) exposed by the opening (Figs. 2A-2O/Fig. 2H, 118A, opening; Figs. 2A-2O/Fig. 2I, 104S, upper surface of the axial portions of the sacrificial gate structures, 104) to expose the gate sacrificial layer (annotated Figure 2H);
using the third dielectric layer as a mask (Figs. 2A-2O/Figs. 2F-2H, 116+118, protective insulating material followed by patterned etch mask) to selectively remove (Figs. 2A-2O/Fig. 2J, [Col. 7, Lines 29-36]) the gate sacrificial layer (annotated Figure 2H) exposed by the opening (Figs. 2A-2O/Fig. 2H, 118A, opening; Figs. 2A-2O/Fig. 2I, 104S, upper surface of the axial portions of the sacrificial gate structures, 104) to form the gate cutting groove (Figs. 2A-2O, 120, gate-cut cavities).
ZHANG as modified by XIE does not explicitly disclose the method of manufacturing a semiconductor device, wherein, using the third dielectric layer as a mask to selectively remove a portion of the sidewall structure exposed by the opening to form a sidewall support structure.
TANG teaches the method of manufacturing a semiconductor device (Fig. 25, S101-S111, fabrication process of a semiconductor device, [0014]), wherein, using the third dielectric layer as a mask (Figs. 13-15, 290, second dielectric layer) to selectively remove a portion of the sidewall structure (Figs. 13-16, 261, second sidewall spacers may be removed by etching process, [0080]) exposed (Fig. 14, contact holes 301 may expose the sidewall surfaces of the first sidewall spacers, 231 and the second sidewall spacers, 261, [0075]) by the opening (Fig. 14, 301, contact holes) to form a sidewall support structure (Fig. 16, 310, air gap spacers, [0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHANG as modified by XIE to incorporate the teachings of TANG such that the method of manufacturing a semiconductor device, wherein, using the third dielectric layer as a mask to selectively remove a portion of the sidewall structure exposed by the opening to form a sidewall support structure, so that the air gap spacers, may reduce the parasitic capacitance between the gate structure, and the conductive plugs (TANG, [0080]).
Regarding Claim 9, ZHANG as modified by XIE and TANG teaches the method of manufacturing a semiconductor device according to claim 7.
TANG further teaches the method for manufacturing the semiconductor device (Fig. 25, S101-S111, fabrication process of a semiconductor device, [0014]), wherein, in a step (Fig. 25, S111, [0079]) of using the third dielectric layer as the mask (Figs. 13-15, 290, second dielectric layer) to selectively remove the portion of the sidewall structure (Figs. 13-16, 261, second sidewall spacers may be removed by etching process, [0080]) exposed (Fig. 14, contact holes 301 may expose the sidewall surfaces of the first sidewall spacers, 231 and the second sidewall spacers, 261, [0075]) by the opening (Fig. 14, 301, contact holes) to form a sidewall supporting structure (Fig. 16, 310, air gap spacers, [0080]), a top surface (annotated Figs. 15/16) of the sidewall support structure (Figs. 13-16, 261/301, second sidewall spacers/air gap spacers) is higher than or flush with (annotated Figs. 15/16) a bottom surface (annotated Figs. 15/16) of the second dielectric layer (Figs. 15-16, 270, first dielectric layer).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9916982 B1 – Figure 11
STATEMENT OF RELEVANCE – A top view of the substrate portion at a fabrication stage, wherein the functional gate structures, 44 have ends 43 that are spaced apart from each other at the location of the gate cut.
US 9799564 B1 – Figure 28
STATEMENT OF RELEVANCE – A flowchart of an exemplary fabrication process, for filling the contact holes by etching the dielectric layer between the two neighboring gate structures.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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