Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Applicant’s IDS submitted on 5/8/24 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
TRENCH GATE INSULATED GATE BIPOLAR TRANSISTOR WITH AN EMITTER RESISTANCE PORTION BETWEEN THE LOWER END OF THE EMITTER AND THE EMITTER ELECTRODE
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 20: Claim 20 depends form claim 19. In claim 19 the emitter region has a first emitter region and a second emitter region. Claim 20 recites that the emitter region is under the second emitter portion, it is unclear how the emitter region (the whole region) can be under a part of the region (the second emitter portion).
For purposes of examination this claim has been interpreted as the “a third emitter region is provided under the second emitter portion.”
Regarding claim 22: Claim 22 recites “an upper end of the gate conductive portion is arranged facing the third emitter portion” this claim requires the third emitter region to go over the upper end of the gate region. This is unclear because it depends from claim 19 which recites an emitter region in contact with the upper surface, and a resistance region under the emitter region and claim 20 adds a third emitter region under the resistance region. The third emitter portion cannot be under the resistance region and over the gate.
For purposes of examination this claim has been interpreted having the third emitter region below the resistance as this interpretation agrees with the claims from which it depends.
Claims 21-26 have been included because they depend from claim 20 and therefore include all of the limitations of claim 20 and therefore have the same indefinite problems.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Senoo, US 20130015493 A1, hereafter Senoo, in view of Francis et al., US 20030201454 A1, hereafter Francis, and Takeuchi et al., US 20210384343 A1, hereafter Takeuchi.
Regarding claim 1, Senoo discloses:
A semiconductor device (Senoo, Figure 1, semiconductor apparatus 10) comprising a semiconductor substrate (Senoo, Figure 1, semiconductor substrate 12) which has an upper surface and a lower surface and is provided with a drift region of a first conductivity type (Senoo, Figure 1, drift region 112, disclosed in [0048] as n-type, a first conductivity type), the semiconductor device comprising:
a gate trench portion having a longitudinal side in a first direction at the upper surface of the semiconductor substrate (Senoo, Figure 1, shows a plurality of trenches as disclosed in [0042], and they are gate trenches as they contain gate insulating film 82 and gate electrode 80);
an emitter region of the first conductivity type (Senoo, Figure 1, emitter region 102) which is provided to be exposed on the upper surface in the semiconductor substrate (Senoo, Figure 1, emitter region 102 is in contact with upper surface 14), is in contact with the gate trench portion (Senoo, Figure 5 and 6, [0064] show the trenches formed in contact with the emitter region), and has a length in the first direction that is longer than a length in a second direction orthogonal to the first direction;
a base region of a second conductivity type (Senoo, Figure 1, lower body region 110, doped p-type, a second conductivity type) which is provided between the emitter region and the drift region and is in contact with the gate trench portion (Senoo, Figure 1, shows 110 in contact with the gate trenches):
an emitter electrode provided above the upper surface of the semiconductor substrate (Senoo, Figure 1, emitter electrode 50); and
a resistance portion provided between a lower end of the emitter region and the emitter electrode.
Senoo fails to disclose the following limitations: (parenthetical added for clarity)
(the emitter region) has a length in the first direction that is longer than a length in a second direction orthogonal to the first direction;
a resistance portion provided between a lower end of the emitter region and the emitter electrode.
Francis discloses the following limitation:
(the emitter region) has a length in the first direction that is longer than a length in a second direction orthogonal to the first direction (Francis, Figure 1A and [0024]-[0028] discloses an emitter with a length in the first direction (Figure 1A, X) of 2 to 4 microns and a width in the second direction of 1.5 to 3 microns (Figure 1A, Y) plus 0.3 to 1.0 microns (Figure 1A, Z));
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to have applied the teaching so Francis to the device of Senoo and to therefore have made the emitter with an increased depth, doing so is taught by Francis to control threshold voltage and permit the use of a very deep P-+ region without danger of it encroaching into the channel (which would increase VT) [0005]).
The combination of Senoo and Francis fail to disclose the following limitations:
a resistance portion provided between a lower end of the emitter region and the emitter electrode.
Takeuchi discloses the following limitations:
a resistance portion provided between a lower end of the emitter region and the emitter electrode (Takeuchi, Figure 1, first source region 8a, and [0078] which discloses that 8a provides resistance to inhibit Ron from deteriorating and [0164] which discloses that teaching can also be used in an IGBT).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Takeuchi to the device of Senoo and Francis and to therefore have included a resistance portion in the emitter because Takeuchi teaches that such a resistance region increases channel density in the device and allows a large current to flow (Takeuchi, [0003]).
Regarding claim 19, the combination of Senoo, Francis and Takeuchi disclose:
The semiconductor device according to claim 1, wherein the emitter region has:
a first emitter portion in contact with the upper surface of the semiconductor substrate (Takeuchi, Figure 1, second source region 8b); and
a second emitter portion (Takeuchi, Figure 1, first source region 8a) provided under the first emitter portion and having a lower doping concentration than the first emitter portion (Takeuchi, Figure 1, 8b is N+-type and 8a is N-type), wherein
the second emitter portion has any of: a flat portion where a doping concentration distribution in a depth direction is flat (Takeuchi, [0072] discloses first source region 8a has a concentration of 1.0×1016/cm3 and the layer is an epitaxial layer [0053], a technique that produces a flat distribution); a valley portion where a doping concentration exhibits a local minimum value in a depth direction; or a peak where a doping concentration exhibits a local maximum value and is lower than that of the first emitter portion in a depth direction (Takeuchi, [0072] discloses a higher doping concentration for the second source region 8b, a doping concentration of 1.0×1019/cm3), and
the second emitter portion is the resistance portion (Takeuchi, first source region 8a (second emitter portion) has a lower doping concentration that second source region 8b (first emitter portion), this make the first source region more resistive than the second region, making it a resistance portion).
Claims 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Senoo, Francis and Takeuchi as applied to claim 19 above, and further in view of Conzelmann et al, US 5990539 A, hereafter Conzelmann.
Regarding claim 20, the combination of Senoo, Francis and Takeuchi fail to disclose:
The semiconductor device according to claim 19, wherein
the emitter region is provided under the second emitter portion and further has a third emitter portion having a higher doping concentration than the second emitter portion.
Conzelmann discloses:
the emitter region is provided under the second emitter portion and further has a third emitter portion having a higher doping concentration than the second emitter portion (Conzelmann, Figure 2, discloses partial-emitter region 83, is under emitter resistor 87, and ion-implanted area 88).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have formed an integrated emitter resistor with higher doped regions both above and below the resistive layer, doing so is taught by Conzelmann and “The integrated emitter resistors cause a stabilized, uniform current distribution both over the various partial-emitter regions, and within the partial-emitter regions, and bring about an improved current carrying capacity, as well as improved high-frequency properties.” Because resistance goes up as doping level goes down, the third emitter layer would have a higher doping concentration than the second layer (the resistor layer).
Regarding claim 21, Senoo, Francis, Takeuchi, and Conzelmann fail to specifically disclose:
The semiconductor device according to claim 20, wherein
the third emitter portion has a lower doping concentration than the first emitter portion.
In the combination of Senoo, Francis, Takeuchi, and Conzelmann, fail to specifically disclose the doping concentrations of the device, However, the first emitter region (Conzelmann, 88), has a charge carrier density sufficient to ensure a contact free of a barrier layer, therefore region is heavily doped, and the third emitter portion (Conzelmann, 83) is a device layer. It would have been obvious to one of ordinary skill in the art to have formed the device layer with dopant concentration lower than that of the region implanted for the contact because heavily doped silicon improves the ability to make good, ohmic contacts, but also degrades the semiconductor properties of the silicon. Since the emitter is part of the device one of ordinary skill would not heavily dope this region as semiconductor properties would be wanted in the device regions, the contact region would be heavily doped so that an ohmic contact can be formed to the device.
Regarding claim 22, Senoo, Francis, Takeuchi, and Conzelmann disclose:
The semiconductor device according to claim 20, wherein the gate trench portion has:
a gate conductive portion provided inside the semiconductor substrate (Senoo, Figure 1, gate electrode 80 is inside substrate 12); and
a gate dielectric film provided between the gate conductive portion and the semiconductor substrate (Senoo, Figure 1, gate insulating film 82), wherein
an upper end of the gate conductive portion is arranged facing the third emitter portion (Senoo as modified by Francis, Takeuchi, and Conzelmann disclose a resistance layer between two higher doped layers aside the upper end (a face) of the gate conductor).
Regarding claim 23, Senoo, Francis, Takeuchi, and Conzelmann disclose:
The semiconductor device according to claim 20, wherein
the emitter electrode is in contact with the first emitter portion and is not in contact with the second emitter portion and the third emitter portion (Conzelmann, Figure 2, emitter-metal contact 89 contacts only ion-implanted area 88).
Allowable Subject Matter
Claims 2-18 and 24-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding clam 2: Claim 2 would be allowable is rewritten in independent form. This claim would be allowable if written in independent form because the closest prior art does not appear to disclose, alone or in combination, a resistance portion between the emitter region and the emitter electrode. Claim 1 requires the emitter region is exposed on the upper surface of the semiconductor surface. The closest prior art is Senoo. Senoo disclose an emitter region exposed on the upper surface of the substrate, but fails to disclose a resistance portion between this emitter region and the emitter electrode. The other prior art of record fails to remedy this deficiency.
Regarding claim 3-18. Claims 3-18 depend from and therefore include all of the limitations claim 2, and are therefore allowable for the same reasons.
Regarding claim 24. Claim 24 would be allowable is rewritten in independent form and overcoming the 112 rejections. This claim would be allowable because the closest prior art does not appear to disclose, alone or in combination, the limitations of a first emitter portion in contact with a trench contact portion and the second and third emitter portions are not in contact with the trench contact portion. The closest prior art is Senoo. Senoo disclose an emitter region in contact with the side of the gate contact, as modified by Francis, Takeuchi, and Conzelmann all three emitter regions would contact the side of the gate contact.
Claim 25-26 both depend from claim 24 and therefore include all of the limitations of the claim and would therefore be allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoshikawa, US 12690209 B2, by same applicant and inventor, drawn to a similar device, requires low doped resistive layer on top of a highly doped layer.
Hoshi, US 20260143790 A1, an after filed application, drawn to similar device with a three layer emitter, where the resistance is between two higher doped layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 10-2 ET.
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/LINDA J. FLECK/ Examiner, Art Unit 2812
/William B Partridge/ Supervisory Patent Examiner, Art Unit 2812
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