Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I (claims 1-12) in the reply filed on May 11, 2026, is acknowledged. The traversal is on the ground that there is no undue burden to examine all of the original claims, 1-19, simultaneously. This is not found persuasive because the fact that the process of claim 13 is not the only process by which the device of claim 1 can be manufactured means that prior art that teaches the claimed device may not necessarily teach the claimed process for manufacturing said device, thus creating a search burden.
The requirement is still deemed proper and is therefore made FINAL.
Claims 13-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on May 11, 2026.
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Fig. 2 of J. A. Kim, reproduced with annotations added by the examiner.
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Fig. 3A of J. A. Kim, reproduced with annotations added by the examiner.
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Mockup of rearrangement of boundaries of insulating layers for the purposes of rejections of claims 3-7, prepared by the examiner based on Fig. 3A of J. A. Kim. While this figure only shows the bit line structure 135_1, a similar rearrangement of the boundaries of the insulating layers near the bit line structure 135_2 can be done because the structure of these spacer structures is similar, as shown in Fig. 2 of J. A. Kim.
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Fig. 3A of S. H. Kim, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jin A. Kim et. al., Pub. No. US 2022/0102353, hereafter referred to as J. A. Kim, in view of Sung Hwan Kim et. al., Pub. No. US 2022/0415793, hereafter referred to as S. H. Kim.
Regarding claim 1, J. A. Kim teaches “A semiconductor structure” (J. A. Kim [0002]; Figs. 2 and 3A, reproduced above with annotations added by the examiner), “comprising: a substrate” (J. A. Kim [0019]; Fig. 2, substrate 100); “a plurality of stack structures located on the substrate” (J. A. Kim [0019]; Fig. 2, bit line structures 135_1 and 135_2; note that the bit line structures 135_1 and 135_2 are disposed over the substrate 100) “and separated from each other” (J. A. Kim Fig. 2; note that the bit line structures 135_1 and 135_2 are separated), “wherein the plurality of stack structures comprise a bit line stack structure” (J. A. Kim Fig. 2, bit line structure 135_1) “and a conductive line stack structure” (J. A. Kim Fig. 2, bit line structure 135_2); “a plurality of first spacers located on sidewalls of the plurality of stack structures” (J. A. Kim [0019]; Fig. 2, spacer structures 150; note that the each of the spacer structures 150 contact one of the bit line structures 135_1 or 135_2); “a contact located on the substrate” (J. A. Kim [0019]; Fig. 2, buried contact 140; note that the buried contact 140 is disposed over the substrate) “between two of the adjacent first spacers” (J. A. Kim Fig. 2; note that the buried contact 140 is located between adjacent spacer structures 150); “and a plurality of second spacers” (J. A. Kim [0053]; Figs. 2 and 3A, air spacer 150A) “located on the plurality of first spacers” (J. A. Kim Figs. 2 and 3A; note that the air spacer 150A lies on top of portions of the spacer structure 150), but does not teach “wherein each of the plurality of first spacers comprises an oxide layer” and “wherein a top surface of the oxide layer is not higher than a top surface of the contact”.
S. H. Kim, on the other hand, teaches similar spacer structures (S. H. Kim [0033]; Fig. 3A, spacer structures 150) and further teaches that the layers 151-153 (S. H. Kim [0054]; Fig. 3A) of these spacer structures may be made of silicon oxide and/or silicon nitride (S. H. Kim [0059]: “The first spacers 151, the second spacers 152, and the third spacers 153 may include or may be formed of at least one of silicon oxide, silicon oxynitride, silicon nitride, and a combination thereof, but the present disclosure is not limited thereto. Alternatively, the first spacers 151, the second spacers 152, and the third spacers 153 may include or may be formed of silicon nitride.”).
The possible materials of the spacer structures of S. H. Kim can be incorporated into the device of J. A. Kim by making the second spacer 152 (J. A. Kim [0053]; Figs. 2 and 3A) out of silicon oxide. The combined device teaches “wherein each of the plurality of first spacers” (J. A. Kim [0033]; Figs. 2 and 3A, spacer structures 150) “comprises an oxide layer” (J. A. Kim [0053]; Figs. 2 and 3A, second spacers 152; S. H. Kim [0059]), “wherein a top surface of the oxide layer is not higher than a top surface of the contact” (J. A. Kim Fig. 2; note that the top surface of the second spacer 152 is lower than the top surface of the buried contact 140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the second spacer of J. A. Kim out of silicon oxide as suggested by S. H. Kim because silicon oxide can function as an insulator and it is a simple combination of elements of the two disclosures.
Regarding claim 2, the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 further teaches “The semiconductor structure according to claim 1, wherein each of the plurality of first spacers further comprises: a first nitride layer” (J. A. Kim [0053]; Figs. 2 and 3A, fourth spacer 154; also see [0069]: “For example… the… fourth spacers… 154 may be made of silicon nitride, but they are not limited thereto.”) “located between the oxide layer and the contact” (J. A. Kim Figs. 2 and 3A; note that the fourth spacer 154 is located between the second spacer 152 and the buried contact 140).
Regarding claim 3, the combined device of J. A. Kim and S. H. Kim as applied to claim 1 teaches “The semiconductor structure according to claim 2”, but does not teach “wherein a top surface of the first nitride layer is not higher than the top surface of the contact.”
S. H. Kim, on the other hand, teaches similar spacer structures (S. H. Kim [0033]; Fig. 3A, spacer structures 150) and further teaches that the layers 151-153 (S. H. Kim [0054]; Fig. 3A) of these spacer structures may be made of silicon oxide and/or silicon nitride (S. H. Kim [0059]), as pointed out in the discussion of claim 1.
The possible materials of the spacer structures of S. H. Kim can be incorporated into the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 by making the first spacer 151 (J. A. Kim [0053]; Figs. 2 and 3A) out of silicon nitride, and then combining the first spacer 151 and the third spacer 153 (J. A. Kim [0053]; Figs. 2 and 3A) into a single spacer and splitting the fourth spacer 154 (J. A. Kim [0053]; Figs. 2 and 3A) into two portions, as illustrated in the mockup prepared by the examiner based on J. A. Kim Fig. 3A shown above. Note that, in the combination just described, all three of the first, third, and fourth spacers 151, 153, and 154 are made of the same material (i.e., silicon nitride), and thus the borders among the various spacers become arbitrary. The combined device just described teaches “wherein a top surface of the first nitride layer” (lower portion of the fourth spacer 154 shown in the mockup based on J. A. Kim Fig. 3A) “is not higher than the top surface of the contact” (note that the top surface of the lower portion of the spacer 154 shown in the mockup based on J. A. Kim Fig. 3A is lower than the top surface of the buried contact 140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the first spacer of the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 out of silicon nitride as suggested by S. H. Kim because silicon nitride can function as an insulator and it is a simple combination of elements of the two disclosures.
Regarding claim 4, the combined device of J. A. Kim and S. H. Kim as applied to claim 1 further teaches “The semiconductor structure according to claim 2”, but does not teach “wherein each of the plurality of first spacers further comprises: a second nitride layer located between the oxide layer and the corresponding stack structure.”
S. H. Kim, on the other hand, teaches similar spacer structures (S. H. Kim [0033]; Fig. 3A, spacer structures 150) and further teaches that the layers 151-153 (S. H. Kim [0054]; Fig. 3A) of these spacer structures may be made of silicon oxide and/or silicon nitride (S. H. Kim [0059]), as pointed out in the discussion of claim 1.
The possible materials of the spacer structures of S. H. Kim can be incorporated into the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 by making the first spacer 151 (J. A. Kim [0053]; Figs. 2 and 3A) out of silicon nitride, and then combining the first spacer 151 and the third spacer 153 (J. A. Kim [0053]; Figs. 2 and 3A) into a single spacer and splitting the fourth spacer 154 (J. A. Kim [0053]; Figs. 2 and 3A) into two portions, as illustrated in the mockup prepared by the examiner based on J. A. Kim Fig. 3A shown above. Note that, in the combination just described, all three of the first, third, and fourth spacers 151, 153, and 154 are made of the same material (i.e., silicon nitride), and thus the borders among the various spacers become arbitrary. The combined device just described teaches “wherein each of the plurality of first spacers further comprises: a second nitride layer” (J. A. Kim Figs. 2 and 3A; first and third spacers 151 and 153; also see mockup based on J. A. Kim Fig. 3A for an illustration of this combination) “located between the oxide layer and the corresponding stack structure” (J. A. Kim Figs. 2 and 3A; note that the first and third spacers 151 and 153 are between the second spacer 152 and the bit line structures 135_1 and 135_2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the first spacer of the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 out of silicon nitride as suggested by S. H. Kim because silicon nitride can function as an insulator and it is a simple combination of elements of the two disclosures.
Regarding claim 5, the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 4 further teaches “The semiconductor structure according to claim 4, wherein a top surface of the second nitride layer is higher than the top surface of the contact” (J. A. Kim Fig. 2; note that the top surface of the third spacer 153 is higher than the top surface of the buried contact 140).
Regarding claim 6, the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 4 further teaches “The semiconductor structure according to claim 4, wherein a portion of the second nitride layer is located directly under a silicon oxide layer” (J. A. Kim Figs. 2 and 3A; note that the bottom portion of the first spacer 151_1 lies beneath the second spacer 152, which is made of silicon oxide).
Regarding claim 7, the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 4 further teaches “The semiconductor structure according to claim 4, wherein a portion of the second nitride layer is located between the corresponding second spacer and the corresponding stack structure” (J. A. Kim Figs. 2 and 3A; note that third spacer 153 lies between the air spacer 150A and the bit line structures 135_1 and 135_2).
Regarding claim 8, the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 further teaches “The semiconductor structure according to claim 1, wherein a width of each of the plurality of second spacers is smaller than a width of each of the plurality of first spacers” (J. A. Kim Figs. 2 and 3A; note the width of the air spacer 150A compared to the width of the combination of the first through fourth spacers, 151-154).
Regarding claim 9, the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 further teaches “The semiconductor structure according to claim 1, further comprising: a landing pad” (J. A. Kim [0022]; Fig. 2, landing pad 160) “located on the contact” (J. A. Kim Fig. 2; note that the landing pad 160 contacts the buried contact 140 through the silicide layer 145), “wherein the landing pad is located on one of the two adjacent first spacers” (J. A. Kim Fig. 2; note that the landing pad 160 contacts the third and fourth spacers 153 and 154) “and one of the two adjacent second spacers” (J. A. Kim Fig. 2; note that the landing pad 160 contacts the air spacer 150A), “and has an opening on one side of the landing pad” (J. A. Kim [0019]; Fig. 2; the opening on the side of the landing pad 160 containing the interlayer insulating layer 180).
Regarding claim 10, the combined device of J. A. Kim and S. H. Kim as applied to claim 1 teaches “The semiconductor structure according to claim 9”, but does not teach “further comprising: a barrier layer located between the landing pad and the contact, between the landing pad and one of the two adjacent first spacers, between the landing pad and the other of the two adjacent first spacers, between the landing pad and one of the two adjacent second spacers, and between the landing pad and the other of the two adjacent second spacers.”
S. H. Kim, on the other hand, does teach “further comprising: a barrier layer” (S. H. Kim [0061]; Fig. 3A, barrier film 165) “located between the landing pad and the contact” (S. H. Kim [0061]; Fig. 3A, note that the barrier film 165 is between the buried contact BC and the landing pad LP), “between the landing pad and one of the two adjacent first spacers” (S. H. Kim Fig. 3A; note that barrier film 165 contacts the corresponding right-hand of the first and third spacers 151 and 153), “between the landing pad and the other of the two adjacent first spacers” (S. H. Kim Fig. 3A; note that barrier film 165 contacts the corresponding left-hand of the third spacers 153), “between the landing pad and one of the two adjacent second spacers” (S. H. Kim Fig. 3A; note that barrier film 165 contacts the corresponding right-hand of the air spacers 150A), “and between the landing pad and the other of the two adjacent second spacers” (S. H. Kim Fig. 3A; note that barrier film 165 contacts the corresponding left-hand of the air spacers 150A).
The barrier films of S. H. Kim disposed on the undersides of the landing pads may be incorporated into the combined device of J. A. Kim and S. H. Kim as applied to claim 1 as similar barrier films on the undersides of the landing pads of said combined device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce a barrier film as taught by S. H. Kim into the combined device of J. A. Kim and S. H. Kim as applied to claim 1 because it would help to prevent interdiffusion of the materials making up the landing pad and the other components that it contacts and it would be a simple combination of elements of the two disclosures.
Regarding claim 11, the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 further teaches “The semiconductor structure according to claim 1, wherein the bit line stack structure” (J. A. Kim Fig. 2, bit line structure 135_1) “comprises: a bit line contact located on the substrate” (J. A. Kim [0019]; Figs. 2 and 3A, direct contact 136; note that the direct contact 136 lies on the substrate 100); “and a bit line located on the bit line contact” (J. A. Kim [0038]; Figs. 2 and 3A, third conductive layer 133; note that the third conductive layer 133 lies above the direct contact 136 and contacts it through the second conductive layer 132).
Regarding claim 12, the combined device of J. A. Kim and S. H. Kim described in the discussion of claim 1 further teaches “The semiconductor structure according to claim 1, wherein the conductive line stack structure” (J. A. Kim Fig. 2, bit line structure 135_2) “comprises: a dielectric layer located on the substrate” (J. A. Kim [0019]; Fig. 2, insulating pattern 120; note that the insulating pattern 120 lies on the substrate 100); “a first conductive layer located on the dielectric layer” (J. A. Kim [0038]; Fig. 2, first conductive layer 131; note that the first conductive layer 131 is disposed on top of the insulating pattern 120); “and a second conductive layer located on the first conductive layer” (J. A. Kim [0038]; Fig. 2, third conductive layer 133; note that the third conductive layer 133 lies above the first conductive layer 131 and contacts it through the second conductive layer 132).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT EMIL THROCKMORTON whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 12 PM and 1 PM - 5:30 PM ET Monday-Thursday, 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN H LOKE can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./Examiner,
Art Unit 2818
/Steven Loke/
SPE, AU 2818
Prosecution Insights