Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/08/2024, 05/28/2024, 9/16/2024,9/27/2024,02/18/2025,03/20/2025, and 09/17/2025 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 24 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 16. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Examiner suggests changing dependency of claim 24 to claim 19, instead of 11
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Takeuchi et al, US 11329154 B2
Takeuchi teaches:
A double-diffused MOS (DMOS) device comprising:
a semiconductor layer (130) having a first conductivity type;
a drift region (126) of a second conductivity type in the semiconductor layer; spaced-apart source (122) and drain (123) regions in the semiconductor layer; Figure 12
a first superlattice (125) on the semiconductor layer, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; (column 5, line 19- column 6, line 23)
a gate (124) above the first superlattice; and
a field plate layer (124) adjacent the drift region and configured to deplete the drift region. Figure 12
Note: Takeuchi shows in e.g. Fig. 12 that the gate 124 extends over the drift region 126, i.e. (a field plate) which can be configured to deplete the drain region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi as applied to claim 1 above, and further in view of Mears et al, US 9 406 753 B2.
Takeuchi fails to teach:
The DMOS device of claim 1 further comprising a second superlattice in the semiconductor layer beneath the drift region, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
The DMOS device of claim 2 further comprising at least one resurf region in the substrate below the second superlattice.
Mears teaches:
(44) It should be noted that while specific parameters (e.g., dimensions, etc.) and materials are provided in the examples set forth herein, other suitable parameters and materials may be used in different embodiments, as will be appreciated by those skilled in the art. For example, the depletion layer stack or quasi-BOX need not be used in both of the NMOS and PMOS devices (e.g., it may be used in one or the other). Moreover, more than one P-N junction may be included in a stack. That is, additional superlattice layers 125 and doped semiconductor layers may be included in the stack, if desired. (i.e. a second superlattice).
Takeuchi teaches claim 3:
at least one resurf region "P-RESURF" (see Fig. 12)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mears with Takeuchi, because additional superlattice layers may be included in the stack (para 44, Mears)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi and Mears as applied to claim 3 above, and further in view of You et al, US 10 998 416 B2.
The above references fail to teach:
4. The DMOS device of claim 3 wherein the at least one resurf region comprises a lower resurf region, and an upper resurf region between the lower resurf region and the second superlattice.
You teaches:
(30) Referring now to FIG. 4, shown is a cross-sectional view of a third example laterally diffused metal oxide semiconductor device, in accordance with embodiments of the present invention. In this particular example, semiconductor device 400 may also include an isolation layer located in the base layer and below the reduced surface field effect layer. The isolation layer can isolate the reduced surface field effect layer from the base layer to facilitate high voltage application of semiconductor device 400. In this example, the isolation layer may be third buried layer NBL of the N-type doped located in high voltage well HVNW and located below buried layer PBL, and the doping concentration of the third buried layer NBL can be greater than that of the high voltage well HVNW. Similarly, the isolation layer described in semiconductor device 400 may also be disposed below the reduced surface field effect layer in example semiconductor device 300.
Therefore, it would have been obvious to one of ordinary skill in the art to combine the above references, because alternating P- and N-type layers result in a resurf effect.
Claim(s) 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi.
Takeuchi teaches:
a cap layer on the first superlattice (column 6, lines 24-29.)
and discloses a body implant 132 (column 11, line 65)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi as applied to claim 1 above, and further in view of You et al, US 10 998 416 B2.
Takeuchi fails to teach:
8. The DMOS device of claim 1 wherein the gate comprises a gate dielectric layer on the semiconductor layer and gate electrode layer on the gate dielectric layer; and wherein the gate dielectric layer has first and second portions, with the second portion being thicker than the first portion.
You teaches:
(31) Referring now to FIG. 5, shown is a cross-sectional view of a fourth example laterally diffused metal oxide semiconductor device, in accordance with embodiments of the present invention. In this particular example, semiconductor device 200 may also include a second conductor. The second conductor may only be located on the thick oxide layer Oxide, and the first conductor can be only located on the first dielectric layer. The first and second conductors may be spatially isolated, whereby the spatial isolation is that the first and second conductors are not in contact with each other in a spatial position and are spaced apart from each other.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because the different thicknesses provide improved protection from shorting.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi.
Takeuchi teaches:
(28) In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
Claim(s) 11, 12 and 14,15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi and further in view of Mears et al, US 9 406 753 B2.
Takeuchi teaches:
A double-diffused MOS (DMOS) device comprising:
a semiconductor layer (130) having a first conductivity type;
a drift region (126) of a second conductivity type in the semiconductor layer; spaced-apart source (122) and drain (123) regions in the semiconductor layer; Figure 12
a first superlattice (125) on the semiconductor layer, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; (column 5, line 19- column 6, line 23)
a gate (124) above the first superlattice; and
a field plate layer (124) adjacent the drift region and configured to deplete the drift region. Figure 12
Note: Takeuchi shows in e.g. Fig. 12 that the gate 124 extends over the drift region 126, i.e. (a field plate) which can be configured to deplete the drain region.
Takeuchi fails to teach:
further comprising a second superlattice in the semiconductor layer beneath the drift region, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Mears teaches:
(44) It should be noted that while specific parameters (e.g., dimensions, etc.) and materials are provided in the examples set forth herein, other suitable parameters and materials may be used in different embodiments, as will be appreciated by those skilled in the art. For example, the depletion layer stack or quasi-BOX need not be used in both of the NMOS and PMOS devices (e.g., it may be used in one or the other). Moreover, more than one P-N junction may be included in a stack. That is, additional superlattice layers 125 and doped semiconductor layers may be included in the stack, if desired. (i.e. a second superlattice).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mears with Takeuchi, because additional superlattice layers may be included in the stack (para 44, Mears)
Takeuchi teaches claim 12:
at least one resurf region "P-RESURF" (see Fig. 12)
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi and Mears as applied to claim 11 above, and further in view of You et al, US 10 998 416 B2.
The above references fail to teach:
13. The DMOS device of claim 12 wherein the at least one resurf region comprises a lower resurf region, and an upper resurf region between the lower resurf region and the second superlattice.
You teaches:
(30) Referring now to FIG. 4, shown is a cross-sectional view of a third example laterally diffused metal oxide semiconductor device, in accordance with embodiments of the present invention. In this particular example, semiconductor device 400 may also include an isolation layer located in the base layer and below the reduced surface field effect layer. The isolation layer can isolate the reduced surface field effect layer from the base layer to facilitate high voltage application of semiconductor device 400. In this example, the isolation layer may be third buried layer NBL of the N-type doped located in high voltage well HVNW and located below buried layer PBL, and the doping concentration of the third buried layer NBL can be greater than that of the high voltage well HVNW. Similarly, the isolation layer described in semiconductor device 400 may also be disposed below the reduced surface field effect layer in example semiconductor device 300.
Therefore, it would have been obvious to one of ordinary skill in the art to combine the above references, because alternating P- and N-type layers result in a resurf effect.
In regards to claims 14 and 15,Takeuchi teaches:
a cap layer on the first superlattice (column 6, lines 24-29.)
and discloses a body implant 132 (column 11, line 65)
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi and Mears as applied to claim 11 above, and further in view of You et al, US 10 998 416 B2.
Takeuchi fails to teach:
16. The DMOS device of claim 15 wherein the gate comprises a gate dielectric layer on the semiconductor layer and gate electrode layer on the gate dielectric layer; and wherein the gate dielectric layer has first and second portions, with the second portion being thicker than the first portion.
You teaches:
(31) Referring now to FIG. 5, shown is a cross-sectional view of a fourth example laterally diffused metal oxide semiconductor device, in accordance with embodiments of the present invention. In this particular example, semiconductor device 200 may also include a second conductor. The second conductor may only be located on the thick oxide layer Oxide, and the first conductor can be only located on the first dielectric layer. The first and second conductors may be spatially isolated, whereby the spatial isolation is that the first and second conductors are not in contact with each other in a spatial position and are spaced apart from each other.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because the different thicknesses provide improved protection from shorting.
Claim(s) 17 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Takeuchi et al, US 11329154 B2
Takeuchi teaches:
A double-diffused MOS (DMOS) device comprising:
a semiconductor layer (130) having a first conductivity type;
a drift region (126) of a second conductivity type in the semiconductor layer; spaced-apart source (122) and drain (123) regions in the semiconductor layer; Figure 12
a first superlattice (125) on the semiconductor layer, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions; (para 33-35)
a gate (124) above the first superlattice; and
a field plate layer (124) adjacent the drift region and configured to deplete the drift region. Figure 12
Note: Takeuchi shows in e.g. Fig. 12 that the gate 124 extends over the drift region 126, i.e. (a field plate) which can be configured to deplete the drain region.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi as applied to claim 17 above, and further in view of Mears et al, US 9 406 753 B2.
Takeuchi fails to teach:
The DMOS device of claim 1 further comprising a second superlattice in the semiconductor layer beneath the drift region, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
The DMOS device of claim 2 further comprising at least one resurf region in the substrate below the second superlattice.
Mears teaches:
(44) It should be noted that while specific parameters (e.g., dimensions, etc.) and materials are provided in the examples set forth herein, other suitable parameters and materials may be used in different embodiments, as will be appreciated by those skilled in the art. For example, the depletion layer stack or quasi-BOX need not be used in both of the NMOS and PMOS devices (e.g., it may be used in one or the other). Moreover, more than one P-N junction may be included in a stack. That is, additional superlattice layers 125 and doped semiconductor layers may be included in the stack, if desired. (i.e. a second superlattice).
Takeuchi teaches claim 3:
at least one resurf region "P-RESURF" (see Fig. 12)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mears with Takeuchi, because additional superlattice layers may be included in the stack (para 44, Mears)
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi and Mears as applied to claim 18 above, and further in view of You et al, US 10 998 416 B2.
The above references fail to teach:
20. The DMOS device of claim 19 wherein the at least one resurf region comprises a lower resurf region, and an upper resurf region between the lower resurf region and the second superlattice.
You teaches:
(30) Referring now to FIG. 4, shown is a cross-sectional view of a third example laterally diffused metal oxide semiconductor device, in accordance with embodiments of the present invention. In this particular example, semiconductor device 400 may also include an isolation layer located in the base layer and below the reduced surface field effect layer. The isolation layer can isolate the reduced surface field effect layer from the base layer to facilitate high voltage application of semiconductor device 400. In this example, the isolation layer may be third buried layer NBL of the N-type doped located in high voltage well HVNW and located below buried layer PBL, and the doping concentration of the third buried layer NBL can be greater than that of the high voltage well HVNW. Similarly, the isolation layer described in semiconductor device 400 may also be disposed below the reduced surface field effect layer in example semiconductor device 300.
Therefore, it would have been obvious to one of ordinary skill in the art to combine the above references, because alternating P- and N-type layers result in a resurf effect.
Claim(s) 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi and Mears.
Takeuchi teaches:
a cap layer on the first superlattice (column 6, lines 24-29.)
and discloses a body implant 132 (column 11, line 65)
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi as applied to claim 1 above, and further in view of You et al, US 10 998 416 B2.
Takeuchi fails to teach:
24. The DMOS device of claim 11 wherein the gate comprises a gate dielectric layer on the semiconductor layer and gate electrode layer on the gate dielectric layer; and wherein the gate dielectric layer has first and second portions, with the second portion being thicker than the first portion.
You teaches:
(31) Referring now to FIG. 5, shown is a cross-sectional view of a fourth example laterally diffused metal oxide semiconductor device, in accordance with embodiments of the present invention. In this particular example, semiconductor device 200 may also include a second conductor. The second conductor may only be located on the thick oxide layer Oxide, and the first conductor can be only located on the first dielectric layer. The first and second conductors may be spatially isolated, whereby the spatial isolation is that the first and second conductors are not in contact with each other in a spatial position and are spaced apart from each other.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because the different thicknesses provide improved protection from shorting.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
