Prosecution Insights
Last updated: August 17, 2026
Application No. 18/658,367

Memory Cells and Integrated Assemblies having Charge-Trapping-Material with Trap-Enhancing-Additive

Non-Final OA §103
Filed
May 08, 2024
Priority
Dec 23, 2019 — divisional of 11/569,390 +1 more
Examiner
BOOTH, RICHARD A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
904 granted / 1055 resolved
+17.7% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
30 currently pending
Career history
1092
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
58.6%
+18.6% vs TC avg
§102
28.2%
-11.8% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1055 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of embodiment 1 in the reply filed on 06/02/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-2, 4-5, 7-17, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dorhout et al., US 2017/0301685 in view of Ramaswamy, U.S. Patent 8,846,516. Dorhout et al. shows the invention substantially as claimed including an integrated assembly, comprising: A stack of alternating first and second levels (18 and 50); the first levels including conductive structures 50 and the second levels being insulative 18 (see fig. 1 and paragraphs 0009-;0025) Channel-material-pillars 34 extending vertically through the stack; and A charge trapping layer 38 extending vertically along the channel-material-pillars (see paragraphs 0008-0026). Dorhout et al. does not expressly disclose first and second charge trapping layers comprising a trap enhancing additive. Ramaswamy discloses forming a charge trapping regions with trap enhancing additives (metals) with a variety of thicknesses and concentrations (see figs. 2-3 and col. 3-line 46 to col. 8-line 5). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form a charge trapping material with metal sites in the primary reference of Dorhout et al. as suggested by Ramaswamy because improved programming and erase voltages can be facilitated. Regarding the charge trapping layers being formed of a multitude of layers (for example, two or three), note that the claims are directed to the product rather than process and therefore the way in which the device is formed does not render the claims patentable unless it materially affects the final device features. With respect to dependent claims 2, 4-5, 7, 9-13, 15-17, and 20, note that Ramaswamy discloses charge trapping layers with a different distribution of concentrations (see fig. 3). Furthermore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to optimize the particular concentration of the trap enhancing additives to obtain a desired concentration profile (see col. 7-lines 37-39 and col. 5-lines 1-20) and such limitation would not lend patentability to the instant application absent a showing of unexpected results. Moreover, the particular thickness of the various charge trapping layers are also process limitations since the charge trapping region 220 of Ramaswamy can be broken down into an infinite number of smaller regions since the claims fail to disclose any distinguishing features between the different charge trapping “layers”. As to dependent claims 14 and 19, note that in the Ramaswamy reference, portions of the charge trapping layer may not have the trap enhancing additive (see fig. 3). Concerning independent claim 15, note that Ramaswamy discloses different regions of the charge trapping regions where the additives have a higher concentration in one region than another. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kitamura et al., US 2010/0171417 discloses the use of charge trapping additives (see paragraph 0340). Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD A BOOTH/ Primary Examiner, Art Unit 2812 July 23, 2026
Read full office action

Prosecution Timeline

May 08, 2024
Application Filed
Jun 03, 2024
Response after Non-Final Action
Jul 28, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
3y 0m to grant Granted Aug 04, 2026
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
2y 6m to grant Granted Jul 28, 2026
Patent 12696516
SEMICONDUCTOR STRUCTURE WITH TWO AIR GAPS ON TWO SIDES OF A TOP SOURCE-DRAIN MIDDLE-OF-LINE CONTACT VIA
2y 7m to grant Granted Jul 28, 2026
Patent 12690186
STRUCTURE WITH FRONTSIDE AND BACKSIDE DRAMS
3y 7m to grant Granted Jul 21, 2026
Patent 12684767
STRUCTURE WITH BURIED DOPED REGION FOR COUPLING SOURCE LINE CONTACT TO GATE STRUCTURE OF MEMORY CELL
3y 6m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.3%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1055 resolved cases by this examiner. Grant probability derived from career allowance rate.

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