Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al. (US 20200411483 A1) in view of Zhou et al. (US 20160035648 A1) in view of Yoo et al. (US 10510724 B2)
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CLAIM 1. Uzoh in view of Zhou in view of Yoo teach a semiconductor package comprising:
a buffer die 2206 (or bottom most die of the die stack located over 2206. Per applicants disclosure a buffer dies may be anything from an interposer to a memory die) ;
a plurality of semiconductor dies 2202 on the buffer die 2206;
a dummy die 1704 on the plurality of semiconductor dies; and
a mold layer 2206 surrounding the buffer die, the plurality of semiconductor dies, and the dummy die, wherein the dummy die comprises:
an oxide layer 2208 on a bottom surface of the dummy substrate,
wherein at least one of the plurality of semiconductor dies comprises:
a substrate 2202, an upper passivation layer 2208 on a top surface of the substrate, and a lower passivation layer 2208 on a bottom surface of the substrate), wherein the oxide layer is in direct contact with the upper passivation layer of an uppermost one of the plurality of semiconductor dies (See Fig. 22 and ¶95-101, Direct bonding of stacked die has the structure as recited.), and
Uzoh teaches dummy substrates having trenches, however is silent upon wherein the dummy substrate comprises a trench formed in a top surface of the dummy substrate, extended in a first direction and a second direction, and having a shape of checkerboard and wherein a level of a bottom surface of the trench is higher than a level of the bottom surface of the dummy substrate.
At the time of the invention, forming trenches in dummy substrates was a known solution for increasing thermal extraction from the memory chips. Forming trenches in a surface is conventional means for increasing surface area. Both Zhou and Yoo teach analogous stacked memory dies including an upper dummy die that includes trenches with a lower trench surface which is higher than the bottom most surface of the dummy die (i.e. a trench partially though the dummy die). Zhou only depicts a cross sectional view of the trenches but teaches in a silicon dummy die heat sink are known to be beneficial for conducting heat away from the stacked die thought the increased surface area provided by the trenches (Zhou ¶16-17). Yoo, demonstrates in figure 4C providing trenches in a the claimed “checkerboard” pattern when providing a silicon dummy die.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the dummy die of Uzoh with Zhou and Yoo to include surface trenches in a checkerboard pattern, since applying a known technique of forming trenches to increase surface area to a known device ready for improvement to yield predictable results of increasing thermal extraction with increased surface area is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 2. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 1, wherein the buffer die comprises: a first substrate; first upper conductive pads on a top surface of the first substrate; and first lower conductive pads on a bottom surface of the first substrate (Uzoh ¶97, Zou Fig. 1, and Yoo Fig. 1), wherein the at least one of the plurality of semiconductor dies comprises: second upper conductive pads on a top surface of the substrate; and second lower conductive pads on a bottom surface of the substrate, wherein the first upper conductive pads are in contact with the second lower conductive pads of a lowermost one of the plurality of semiconductor dies, respectively, and wherein the first upper conductive pads and the second lower conductive pads are formed of a same material (Uzoh Figs. 17 & 22 demonstrate the arrangement however do not depict pads. Pads are however disclosed to be present as claimed. See Uzoh ¶97. Zou Fig. 1, and Yoo Fig. 1 depict conventionally understood pads, required to electrically connect the stacked die.),.
CLAIM 3. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 1, wherein the at least one of the plurality of semiconductor dies comprises: second upper conductive pads on a top surface of the substrate; and second lower conductive pads on a bottom surface of the substrate, wherein the second upper conductive pads of a lower die of the plurality of semiconductor dies are in contact with the second lower conductive pads of an upper die of the plurality of semiconductor dies, respectively, and wherein the second upper conductive pads and the second lower conductive pads are formed of the same material (Uzoh Figs. 17 & 22, ¶97, Zou Fig. 1, and Yoo Fig. 1).
CLAIM 4. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 1, wherein the buffer die comprises a first penetration via, wherein the at least one of the plurality of semiconductor dies further comprises a second penetration via penetrating the substrate, and wherein the first penetration via and the second penetration via are connected to each other (Uzoh Figs. 17 & 22 do not depict “via” however through vias are expected electrically connections routinely found in stacked die, such as depicted in both Zou Fig. 1, and Yoo Fig. 1)..
CLAIM 5. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 1, wherein the bottom surface of the trench is flat (Zou Fig. 1, Yoo Fig. 4c.).
CLAIM 6. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 1, wherein the bottom surface of the trench is concave (Zou Fig. 1, Yoo Fig. 4c. – a trench by definition is concave, therefore there is no clear structural distinction under BRI.)..
CLAIM 7. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 1, further comprising a heat transfer member configured to fill the trench (This limitation does not provide any clear distinction, as “air” may meet the scope of the claim. Yoo Fig. 3b, demonstrates the molding may fill the trenches.)
CLAIM 8. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 1, wherein the trench is filled with the mold layer (Yoo Fig. 3b, demonstrates the molding may fill the trenches.)
CLAIM 9. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 1, wherein the dummy die has a thickness ranging from about 55 μm to about 550 μm (Uzoh ¶0003 – the recited range is in the conventionally known range of thickness parameters.).
CLAIM 10. Uzoh in view of Zhou in view of Yoo teach a semiconductor package comprising:
a buffer die 2206 (or bottom most die of the die stack located over 2206. Per applicants disclosure a buffer dies may be anything from an interposer to a memory die) ;;
a plurality of memory dies on the buffer die;
a dummy die on the plurality of memory dies; and
a mold layer 2206 surrounding the buffer die, the plurality of memory dies, and the dummy die, wherein the buffer die comprises:
a first substrate;
first upper conductive pads on a top surface of the first substrate (Uzoh Figs. 17 & 22, ¶97, Zou Fig. 1, and Yoo Fig. 1);
first lower conductive pads on a bottom surface of the first substrate; and
a first penetration via penetrating the first substrate (Uzoh Figs. 17 & 22 do not depict “via” however through vias are expected electrically connections routinely found in stacked die, such as depicted in both Zou Fig. 1, and Yoo Fig. 1),
wherein at least one of the plurality of memory dies comprises:
a second substrate (Uzoh Figs. 17 & 22);
second upper conductive pads on a top surface of the second substrate (Uzoh Figs. 17 & 22, ¶97, Zou Fig. 1, and Yoo Fig. 1);
second lower conductive pads on a bottom surface of the second substrate; and a second penetration via penetrating the second substrate (Uzoh Figs. 17 & 22, ¶97, Zou Fig. 1, and Yoo Fig. 1 – Conductive pads and vias are understood to be on the surfaces of the chips in order to provide the required electrical circuit connections though the stack of dies.),
wherein the dummy die comprises:
a third substrate comprising a trench formed in a top surface of the third substrate, an oxide layer on a bottom surface of the third substrate; and wherein the dummy die has a thickness ranging from about 55 μm to about 550 μm (Uzoh ¶0003 – the recited range is in the conventionally known range of thickness parameters.).
Uzoh teaches dummy substrates having trenches, however is silent upon wherein the dummy substrate comprises a trench formed in a top surface of the dummy substrate, extended in a first direction and a second direction, and having a shape of checkerboard and wherein a level of a bottom surface of the trench is higher than a level of the bottom surface of the dummy substrate.
At the time of the invention, forming trenches in dummy substrates was a known solution for increasing thermal extraction from the memory chips. Forming trenches in a surface is conventional means for increasing surface area. Both Zhou and Yoo teach analogous stacked memory dies including an upper dummy die that includes trenches with a lower trench surface which is higher than the bottom most surface of the dummy die (i.e. a trench partially though the dummy die). Zhou only depicts a cross sectional view of the trenches but teaches in a silicon dummy die heat sink are known to be beneficial for conducting heat away from the stacked die thought the increased surface area provided by the trenches (Zhou ¶16-17). Yoo, demonstrates in figure 4C providing trenches in a the claimed “checkerboard” pattern when providing a silicon dummy die.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the dummy die of Uzoh with Zhou and Yoo to include surface trenches in a checkerboard pattern, since applying a known technique of forming trenches to increase surface area to a known device ready for improvement to yield predictable results of increasing thermal extraction with increased surface area is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 11. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 10, wherein the first upper conductive pads are in contact with the second lower conductive pads of a lowermost one of the plurality of memory dies, respectively, and wherein the first upper conductive pads and the second lower conductive pads are formed of a same material (Uzoh Figs. 17 & 22 demonstrate the arrangement however do not depict pads. Pads are however disclosed to be present as claimed. See Uzoh ¶97. Zou Fig. 1, and Yoo Fig. 1 depict conventionally understood pads, required to electrically connect the stacked die.),.
CLAIM 12. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 10, wherein the second upper conductive pads of a lower die of the plurality of memory dies are in contact with the second lower conductive pads of an upper die of the plurality of memory dies, respectively, and wherein the second upper conductive pads and the second lower conductive pads are formed of the same material (Uzoh Figs. 17 & 22 demonstrate the arrangement however do not depict pads. Pads are however disclosed to be present as claimed. See Uzoh ¶97. Zou Fig. 1, and Yoo Fig. 1 depict conventionally understood pads, required to electrically connect the stacked die.),.
CLAIM 13. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 10, wherein the at least one of the plurality of memory dies further comprises: an upper passivation layer 2208 on the top surface of the second substrate, and a lower passivation layer 2208 on the bottom surface of the second substrate, and wherein the oxide layer of the dummy die is in direct contact with the upper passivation layer of an uppermost one of the plurality of memory dies (Uzoh Fig. 22).
CLAIM 14. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 10, wherein the trench has a flat bottom surface (Zou Fig. 1, Yoo Fig. 4c.).
CLAIM 15. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 10, wherein the trench has a concave bottom surface (Zou Fig. 1, Yoo Fig. 4c. – a trench by definition is concave, therefore there is no clear structural distinction under BRI.)..
CLAIM 16. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 10, wherein a bottom surface of the trench is located at a level that is higher than the bottom surface of the third substrate (Zou Fig. 1, Yoo Fig. 4c – This limitation is inherent to a trench that is partially though a substrate penetrating from the upper surface.).
CLAIM 17. Uzoh in view of Zhou in view of Yoo teach a semiconductor package comprising:
a package substrate 2304 (Uzoh Figs. 17, 22 & 23 ; ¶101);
an interposer substrate 2303 on the package substrate 2304 (Uzoh Figs. 17, 22 & 23 ; ¶101);
a first semiconductor chip 2305 on the interposer substrate 2303; and a second semiconductor chip 2305 on the interposer substrate, wherein the first semiconductor chip comprises: a buffer die (e.g. bottom most die of the stack); a plurality of semiconductor dies 2305 on the buffer die 2305; a dummy die on the plurality of semiconductor dies; and a mold layer surrounding the buffer die, the plurality of semiconductor dies, and the dummy die, wherein the dummy die (e.g. upper most die) comprises: an oxide layer on a bottom surface of the dummy substrate, wherein at least one of the plurality of semiconductor dies comprises a substrate,
Uzoh teaches dummy substrates having trenches, however is silent upon wherein the dummy substrate comprises a dummy substrate comprising a trench formed in a top surface of the dummy substrate, extended in a first direction and a second direction, and having a shape of checkerboard; a heat transfer member filling the trench; and wherein a level of a bottom surface of the trench is higher than a level of the bottom surface of the dummy substrate, and wherein the bottom surface of the trench is flat.
At the time of the invention, forming trenches in dummy substrates was a known solution for increasing thermal extraction from the memory chips. Forming trenches in a surface is conventional means for increasing surface area. Both Zhou and Yoo teach analogous stacked memory dies including an upper dummy die that includes trenches with a lower trench surface which is higher than the bottom most surface of the dummy die (i.e. a trench partially though the dummy die). Zhou only depicts a cross sectional view of the trenches but teaches in a silicon dummy die heat sink are known to be beneficial for conducting heat away from the stacked die thought the increased surface area provided by the trenches (Zhou ¶16-17). Yoo, demonstrates in figure 4C providing trenches in a the claimed “checkerboard” pattern when providing a silicon dummy die. Yoo further demonstrates the molding material may further fill the opening of the trench patterns formed in the upper surface of the upper most silicon dummy die. It is further noted, the bottom surface as a trench that only penetrates partially though from an upper surface of a substrate inherently has a bottom most surface which is high than the bottom most surface of the substrate.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the dummy die of Uzoh with Zhou and Yoo to include surface trenches in a checkerboard pattern, since applying a known technique of forming trenches to increase surface area to a known device ready for improvement to yield predictable results of increasing thermal extraction with increased surface area is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 18. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 17, wherein the at least one of the plurality of semiconductor dies comprises: an upper passivation layer on a top surface of the substrate; and a lower passivation layer on a bottom surface of the substrate, wherein the oxide layer of the dummy die is in direct contact with the upper passivation layer of an uppermost one of the plurality of semiconductor dies.
CLAIM 19. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 17, wherein the at least one of the plurality of semiconductor dies comprises: upper conductive pads on a top surface of the substrate; and lower conductive pads on a bottom surface of the substrate, wherein the upper conductive pads of a lower die of the plurality of semiconductor dies are in contact with the lower conductive pads of an upper die of the plurality of semiconductor dies, respectively, and wherein the upper conductive pads and the lower conductive pads are formed of the same material (Uzoh ¶94-97 – pads and vias are not depicted however, are disclosed as common features for connecting front and backsides of the stacked chips, similarly to what is depicted in Zhou and Yoo.).
CLAIM 20. Uzoh in view of Zhou in view of Yoo teach the semiconductor package of claim 17, wherein the dummy die has a thickness ranging from about 55 μm to about 550 μm (Uzoh ¶0003 – the recited range is in the conventionally known range of thickness parameters.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
7/15/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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