DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Muljono et al. US Patent No.: 7,036,055.
Regarding Claim 1, Muljono teaches a semiconductor device (see figure 5, 500) comprising:
a first transmission pad configured to output a data signal (see col.9, ln.19-20 and col.10, ln.8-13 and figure 5, teaching data pad 552 and data signal of the source-synchronous architecture);
a second transmission pad configured to output a clock signal (see col.9, ln.19-20; col.10, ln.8-13 and figure 5, teaching strobe pad 555 and strobe signal of the source-synchronous architecture);
a data transmission circuit connected to the first transmission pad and comprising a data driver configured to generate the data signal (figure 5, data transmission circuit disclosed as elements 520, 550, 551, in which the signal is transmitted through driver output 551, and also 1400 in figure 14, which generates the data signal via flip-flop 520);
a clock transmission circuit connected to the second transmission pad and comprising a clock driver configured to generate the clock signal (figure 5, see elements 522, 553, 554, which are connected to the second transmission pad through output of driver 554; see clock driver 553, or 1400 in figure 14, which generates clock signal by receiving output strobe output flip-flop 520);
a core circuit configured to control the data driver and the clock driver (figure 5, pattern generators 528, 529, 540, 544, or see figure 14, testing control unit 1440 and multiplexer 1430); and
at least one buffer (figure 5, input buffers/drivers, 545, 547, or 1445/1045 pair in figure 14; see col.13, ln. 65-67 and col.14, ln. 1-19), wherein each buffer of the at least one buffer comprises:
an input terminal connected to at least one of an output terminal of the data driver and an output terminal of the clock driver (figure 14, wherein output of 1051 is connected to input of 1445); and
an output terminal connected to the core circuit (see figure 14, wherein output of 1445 is connected through mux 1430 to testing control unit 1440).
Regarding Claim 2, Muljono teaches the semiconductor device of claim 1, further comprising a switch element connected between the input terminal of the at least one buffer and at least one of the output terminal of the data driver and the output terminal of the clock driver (see figure 14, pass gate 1420 and the connection between elements 1051, 1052, and 1445).
Regarding Claim 3, Muljono teaches the semiconductor device of claim 2, further comprising a plurality of switch elements including the switch element, wherein the plurality of switch elements is equal in number to a number of the at least one buffer (see figure 5, 520 and 522, which are switches that correspond in number to the buffers).
Regarding Claim 4, Muljono teaches the semiconductor device of claim 2, further comprising a plurality of switch elements including the switch element, wherein the plurality of switch elements is different from a number of the at least one buffer (see figure 5, 543 is also a switch element, and when considered in addition to 520 and 522, a different number of switches exists in the switch unit from the number of buffers).
Regarding Claim 5, Muljono teaches the semiconductor device of claim 1, wherein the at least one buffer comprises a first buffer connected to the output terminal of the data driver, and a second buffer connected to the output terminal of the clock driver (seen in figure 5 as both the clock and data outputs are connected to buffers 545 and 547).
Regarding Claim 7, Muljono teaches the semiconductor device of claim 5, wherein the core circuit is further configured to: control the data driver to continuously output a voltage corresponding to digital 0 or a voltage corresponding to digital 1 during a predetermined first test time, and verify the data transmission circuit using an output of the first buffer during the predetermined first test time (see [0064], which discusses the digitizing of voltage values during testing).
Regarding Claim 8, Muljono teaches the semiconductor device of claim 5, wherein the core circuit is further configured to: control the clock driver to continuously output a voltage corresponding to digital 0 or a voltage corresponding to digital 1 during a predetermined second test time, and verify the clock transmission circuit using an output of the second buffer during the predetermined second test time (see [0064], which discusses the digitizing of voltage values during testing, which includes an initial test and subsequent tests).
Claim(s) 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Loke et al. US PG Pub. No.: US 2016/0025807.
Regarding Claim 14, Loke teaches a semiconductor package (see figure 4, 410) comprising:
a first semiconductor device comprising a first transmission pad configured to output a data signal and a second transmission pad configured to output a clock signal (figure 4, die1 and figure 2, which illustrates data pad 110 and clock pad 130);
a second semiconductor device comprising a first reception pad configured to receive the data signal and a second reception pad configured to receive the clock signal (figure 4, die2 and figure 1, data pad 120 and clock pad 140);
an intermediate substrate on which the first semiconductor device and the second semiconductor device are mounted (see [0048] and 402, referred to as an interposer), wherein the intermediate substrate comprises a redistribution pattern connecting the first transmission pad with the first reception pad and connecting the second transmission pad with the second reception pad (see [0050] and figure 4, in which cut-view 420 shows a detailed view of interposer 402 and teaches that data and clock forwarding routes are included in the interposer, which encompass the redistribution pattern); and
a package substrate on which the intermediate substrate is mounted (figure 5, in which the package is disposed on a substrate 516), wherein the first semiconductor device comprises:
a first switch element connected between an output terminal of a data driver configured to output the data signal and the first transmission pad (see figure 1, 117 which is a flip-flop acting as a data switch); and
a first buffer connected to the first switch element (see the element labeled ‘Buffer’ which receives a signal from switch 117).
Regarding Claim 15, Loke teaches the semiconductor package of claim 14, wherein the first semiconductor device further comprises: a second switch element connected between an output terminal of a clock driver configured to output the clock signal and the second transmission pad (seen in figure 5); and a second buffer connected to the second switch element and implemented separately from the first buffer (see figure 5 in which the first buffer 545 and first switch 520 are implemented separately from the second buffer 547 and second switch 522).
Regarding Claim 16, Loke teaches the semiconductor package of claim 14, wherein the first semiconductor device further comprises a second switch element connected between an output terminal of a clock driver configured to output the clock signal and the second transmission pad (seen in figure 5), and wherein the second switch element is connected to the first buffer (seen in figure 5).
Allowable Subject Matter
Claims 6, 9-13, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
RE Claim 6, the prior art of record does not disclose or suggest “a first switch element connected between the input terminal of the first buffer and the output terminal of the data driver, and a second switch element connected between the input terminal of the second buffer and the output terminal of the clock driver,” in combination with the other claim limitations.
RE Claim 9, the prior art of record does not disclose or suggest “wherein the core circuit is further configured to stop an operation of the PLL circuit during the predetermined second test time and to control the clock driver to continuously output a voltage corresponding to digital 0 or a voltage corresponding to digital 1 using the DCC circuit,” in combination with the other claim limitations.
RE Claim 10, the prior art of record does not disclose or suggest “wherein the core circuit is further configured to verify the sense amplifier by adjusting an offset cancellation code input to the sense amplifier while activating an offset cancellation function of the sense amplifier,” in combination with the other claim limitations. Claims 11-13 depend from base Claim 10, and therefore these claims are also allowed.
RE Claim 17, the prior art of record does not disclose or suggest “a plurality of bumps in contact with the intermediate substrate and an upper surface of the package substrate, wherein the intermediate substrate is mounted on the upper surface of the package substrate via the plurality of bumps, wherein each of the plurality of microbumps comprises a diameter of 50 micrometers or less,” in combination with the other claim limitations.
Claims 18-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
RE Claim 18, the prior art of record does not disclose or suggest “set one of the first offset cancellation code and the second offset cancellation code to a maximum value and set the other one of the first offset cancellation code and the second offset cancellation code to a minimum value, and identify whether the sense amplifier is defective,” in combination with the other claim limitations. Claims 19-20 depend from base Claim 18, and therefore these claims are also allowed. The closest cited prior art, Muljono et al. US Patent No.: 7,036,055 and Loke et al. US PG Pub. No.: US 2016/0025807 teach structural components claimed in Claim 18, namely the reception pad, sense amplifier, and core circuit. However, these references were silent in teaching the offset cancellation circuitry and corresponding limitations. Mo et al. USPG Pub. No.: US 2013/0088624 teaches an offset cancellation circuit, but is silent in teaching setting a first offset cancellation code and second offset cancellation code to a maximum value and set the other one of the first offset cancellation code and the second offset cancellation code to a minimum value, in the context of the claim language.
Conclusion
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/MICHAEL A HARRISON/Examiner, Art Unit 2852