DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because line 5 includes an extra comma, “first gap filling portion,,”; this should instead read “first gap filling portion,”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The title, “SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE”, should not include any mention of process or method of manufacturing. Instead, we suggest the title, “Semiconductor Package using Co-planar Gap Filling”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 9, 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choo et al (US 2023/0154509 Al; hereinafter, “Choo”) in view of Jeng et al (US 20200091029 A1; hereinafter, “Jeng”) and Cho et al (CN 115706096 A; hereinafter, “Cho”).
Regarding claim 1:
Choo discloses (Figure 12) a semiconductor package comprising;
a buffer die (3110; [0124]);
a plurality of core die blocks (3120, 3130, 3140, 3150; [0124]) sequentially stacked on the buffer die; and
(NOTE: “the plurality of third semiconductor chips” must read “the third semiconductor chip”, otherwise there would be a lack of antecedent basis)
Choo does not disclose a molding member or details within the core dies, therefore, Choo does not disclose the text with the strikethrough limitations.
Cho teaches (in Fig. 1) a molding member 300 that encapsulates a stack of dies, providing structural support.
Jeng teaches a core die block 130a (Fig. 1B; [0018]) comprising:
a first semiconductor chip (132A) having a plurality of first conductive pads (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections) that are exposed from a first upper surface of the first semiconductor chip and a plurality of first bonding pads that are exposed from a first lower surface of the first semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections);
a second semiconductor chip (132B) and a first gap filling portion covering an outer side surface of the second semiconductor chip (a portion of element 140 that directly contacts the outer surface of 132B, see “first gap fill” in Exhibit A below), the second semiconductor chip having a plurality of second conductive pads (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections) that are exposed from a second upper surface of the second semiconductor chip and a plurality of second bonding pads that are exposed from a second lower surface of the second semiconductor chip, the plurality of second bonding pads of the second semiconductor chip being bonded to the plurality of first conductive pads of the first semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections);
a third semiconductor chip (132C) and a second gap filling portion covering an outer side surface of the third semiconductor chip (a portion of element 140 that directly contacts the outer surface of 132C, see “second gap fill” in Exhibit A), the third semiconductor chip having a plurality of third conductive pads (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections) that are exposed from a third upper surface of the third semiconductor chip and a plurality of third bonding pads that are exposed from a third lower surface of the third semiconductor chip, the plurality of third bonding pads of the third semiconductor chip (NOTE: “the plurality of third semiconductor chips” must read “the third semiconductor chip”, otherwise there would be a lack of antecedent basis) being bonded to the plurality of second conductive pads of the second semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections); and
a fourth semiconductor chip (132D) having a plurality of fourth bonding pads that are exposed from a fourth lower surface of the fourth semiconductor chip that is opposite to a fourth upper surface of the fourth semiconductor chip, the plurality of fourth bonding pads being bonded to the plurality of third conductive pads of the third semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choo by incorporating a molding member as taught by Cho to provide structural support for the core die stack. Furthermore, because Choo does not provide the internal structure of the core dies, it would have been obvious to incorporate a core die structure as taught by Jeng to increase the number of chips in Choo’s core dies.
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Regarding Claims 2-7, 9 and 10:
re claim 2, Jeng teaches an outer side surface of the second gap filling portion (Exhibit A, “second gap fill”) is located on the same plane (Exhibit A, “same plane”) as an outer side surface of the first gap filling portion (Exhibit A, “first gap fill”, NOTE: “filing” should read “filling”);
re claim 3, Jeng teaches the outer side surfaces of the first and second gap filling portions (Exhibit A, “first gap fill” and “second gap fill”) are located on the same plane as an outer side surface of the first semiconductor chip and an outer side surface of the fourth semiconductor chip. (Here, “outer surface” is defined relative the center line of the chips and the center of the gap fills);
re claim 4, Choo (in view of Cho and Jeng) does not explicitly disclose a planar area. However, Jeng illustrates (in a plane of Figure 1B) that a first planar area of the first semiconductor chip is equal to a fourth planar area of the fourth semiconductor chip (i.e., the first chip 132A and the fourth chip 132D are shown to have the same/equal area);
re claim 5, Choo (in view of Cho and Jeng) does not explicitly disclose a second and third chip with smaller planar areas than the first planar area, however, the current claim is deemed because process variation in the dicing of chips ready results in slight variations in chip sizes (i.e., when dicing a wafer into a plurality of chips, there would be slight variations in size at least in an atomic, nanometer, etc. scale). Given this process variation, it would have been obvious to a POSITA to place these smaller dies in the middle of stack such that the bottommost die and the topmost dies in the stack provide an overhang for structural support of the gap fills at the outer surfaces of the middle dies. Furthermore, because a clear meaning of “smaller” (i.e., “substantially smaller”, or a specific metric) has not been defined, minute variations during processing render obvious different sizes of dies within each core die.
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re claim 6, Jeng teaches (Exhibit B, Figure 1B) the fourth semiconductor chip further includes a plurality of fourth conductive pads that are exposed from the fourth upper surface. In other words, Jeng teaches that, “The number of the semiconductor dies 132A, 132B, 132C, 132D are not limited to four, and the number can be adjusted according to the actual application.” Therefore, it would have been obvious to provide the upper-most chip, 132D, with conductive pads on its upper surface for electrical connectivity to a subsequent core die, and; Choo discloses (Exhibit B, Fig. 12) the plurality of fourth conductive pads of a first core die block (Exhibit B, “1st core die block”) of the plurality of core die blocks are bonded to a plurality of first bonding pads of a second core die block (Exhibit B, “2nd core die block”) of the plurality of core die blocks.
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re claim 7, Jeng teaches the first semiconductor chip 132A (Fig. 1B) includes a plurality of first through electrodes (Exbibit C above, “first through electrodes”) that electrically connect the plurality of first conductive pads (Exbibit C, “first conductive pads…”) and the plurality of first bonding pads (Exbibit C, “first bonding pads…”),
each of the plurality of second semiconductor chips 132B (Fig. 1B) includes a plurality of second through electrodes (Exbibit C, “second through electrodes”) that electrically connect the plurality of second conductive pads (Exbibit C, “second conductive pads…”) and the plurality of second bonding pads (Exbibit C, “second bonding pads…”), and
each of the plurality of third semiconductor chips includes a plurality of third through electrodes (Exbibit C, “third through electrodes”) that electrically connect the plurality of third conductive pads (Exbibit C, “third conductive pads…”) and the plurality of third bonding pads (Exbibit C, “third bonding pads…”);
re claim 9, Choo discloses a plurality of external connection bumps respectively provided on a plurality of second substrate pads that are exposed from a lower surface of the buffer die. (See Exhibit B, “second substrate pads”); and
re claim 10, Jeng teaches conductive pads made of Copper, Tungsten and other metals, and therefore, it would be obvious to a POSITA to use, for the first to third conductive pads and the first to fourth bonding pads, at least one of Copper (Cu), Aluminum (Al), Tungsten (W), Nickel (Ni), Molybdenum (Mo), Gold (Au), Silver (Ag), Chromium (Cr), Tin (Sn), and Titanium (Ti).
Therefore, claims 2-7, 9 and 10 are rendered obvious by Choo (in view of Cho and Jeng).
Regarding claim 20:
Choo discloses (Figure 12) a semiconductor package comprising;
a buffer die (3110; [0124]) having a first surface and a second surface opposite to the first surface;
a plurality of core die blocks (3120, 3130, 3140, 3150; [0124]) sequentially stacked on the first surface of the buffer die; and
s (NOTE: “chips” should read “chip”, otherwise, there would be a lack of antecedent basis)
Choo does not disclose a molding member or details within the core dies, therefore, Choo does not disclose the text with the strikethrough limitations.
Cho teaches (in Fig. 1) a molding member 300 that encapsulates a stack of dies, providing structural support.
Jeng teaches a core die block 130a (Fig. 1B; [0018]) comprising:
a first semiconductor chip (132A) having a first upper surface and a second lower surface opposite to the first upper surface, the first semiconductor chip having a plurality of first conductive pads (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections) that are exposed from the first upper surface and a plurality of first bonding pads that are exposed from the first lower surface (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections);
a second semiconductor chip (132B) and a first gap filling portion covering an outer side surface of the second semiconductor chip (a portion of element 140 that directly contacts the outer surface of 132B, see “first gap fill” in Exhibit A), the second semiconductor chip having a second upper surface and a second lower surface opposite to the second upper surface, a plurality of second conductive pads that are exposed from the second upper surface and a plurality of second bonding pads that are exposed from the second lower surface (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections), the plurality of second bonding pads of the second semiconductor chip being bonded to the plurality of first conductive pads (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections);
a third semiconductor chip (132C) and a second gap filling portion covering an outer side surface of the third semiconductor chip (a portion of element 140 that directly contacts the outer surface of 132C, see “second gap fill” in Exhibit A), the third semiconductor chip having a third upper surface and a third lower surface opposite to the third upper surface, a plurality of third conductive pads that are exposed from the third upper surface and a plurality of third bonding pads that are exposed from the third lower surface (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections), the plurality of third bonding pads of the third semiconductor chip being bonded to the plurality of second conductive pads (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections) of the second semiconductor chipNOTE: “chips” should read “chip”, otherwise, there would be a lack of antecedent basis); and
a fourth semiconductor chip (132D) having a fourth upper surface and a fourth lower surface opposite to the fourth upper surface, the fourth semiconductor chip having plurality of fourth conductive pads that are exposed from the fourth upper surface and a plurality of fourth bonding pads that are exposed from a fourth lower surface, the plurality of fourth bonding pads being bonded to the plurality of third conductive pads of the third semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections),
wherein the first gap filling portion and the second gap filling portion contact each other (Exhibit A, the “first gap fill” and the “second gap fill” are in contact with each other).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choo by incorporating a molding member as taught by Cho to provide structural support for the core die stack. Furthermore, because Choo does not provide the internal structure of the core dies, it would have been obvious to incorporate a core die structure as taught by Jeng to increase the number of chips in Choo’s core dies.
Claims 11-16, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choo in view Jeng.
Regarding claim 11:
Choo discloses (Figure 12) a semiconductor package comprising;
a buffer die (3110; [0124]) having a first surface and a second surface opposite to the first surface, the buffer die having a plurality of substrate pads that are exposed from the first surface (Exhibit B, see “substrate pads” that are required to make electrical connections);
a plurality of core die blocks (3120, 3130, 3140, 3150; [0124]) sequentially stacked on the buffer die; and
Choo does not disclose details within the core dies, therefore, Choo does not disclose the text with the strikethrough limitations.
Jeng teaches a core die block 130a (Fig. 1B; [0018]) comprising:
a first semiconductor chip (132A) having a plurality of first conductive pads (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections) that are exposed from a first upper surface of the first semiconductor chip and a plurality of first bonding pads that are exposed from a first lower surface of the first semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections);
a second semiconductor chip (132B) and a first gap filling portion covering an outer side surface of the second semiconductor chip (a portion of element 140 that directly contacts the outer surface of 132B, see “first gap fill” in Exhibit A), the second semiconductor chip having a plurality of second conductive pads (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections) that are exposed from a second upper surface of the second semiconductor chip and a plurality of second bonding pads that are exposed from a second lower surface of the second semiconductor chip, the plurality of second bonding pads of the second semiconductor chip being bonded to the plurality of first conductive pads of the first semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections);
a third semiconductor chip (132C) and a second gap filling portion covering an outer side surface of the third semiconductor chip (a portion of element 140 that directly contacts the outer surface of 132C, see “second gap fill” in Exhibit A), the third semiconductor chip having a plurality of third conductive pads (in Figure 1B, [0024], element 134 is a TSV that is included in each chip of the stack; each TSV must have a conductive pad on the upper and lower surfaces in order to provide electrical connections) that are exposed from a third upper surface of the third semiconductor chip and a plurality of third bonding pads that are exposed from a third lower surface of the third semiconductor chip, the plurality of third bonding pads of the third semiconductor chip being bonded to the plurality of second conductive pads of the second semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections);
a fourth semiconductor chip (132D) having a plurality of fourth conducive pads and are exposed from a fourth upper surface of the fourth semiconductor chip and a plurality of fourth bonding pads that are exposed from a fourth lower surface of the fourth semiconductor chip that is opposite to a fourth upper surface of the fourth semiconductor chip, the plurality of fourth bonding pads being bonded to the plurality of third conductive pads of the third semiconductor chip (each TSV is required to have a bonding pad or conductive pad in order to provide electrical connections); and
wherein the plurality of first bonding pads (Exhibit B, “first bonding pads”) of a lowermost core die block (Exhibit B, “1st core die block”) among the plurality of core die blocks are bonded to the plurality of substrate pads (Exhibit B, “second substrate pads”) of the buffer die.
Because Choo does not provide the internal structure of the core dies, it would have been obvious to one of ordinary skill in the art to incorporate a core die structure comprising a stack of multiple dies, as taught by Jeng, to increase the number of chips in Choo’s core dies.
Regarding Claims 12-16, 18 and 19:
re claim 12, Jeng teaches an outer side surface of the second gap filling portion (Exhibit A, “second gap fill”) is located on the same plane (Exhibit A, “same plane”) as an outer side surface of the first gap filling portion (Exhibit A, “first gap fill”, NOTE: “filing” should read “filling”);
re claim 13, Jeng teaches the outer side surfaces of the first and second gap filling portions (Exhibit A, “first gap fill” and “second gap fill”) are located on the same plane as an outer side surface of the first semiconductor chip and an outer side surface of the fourth semiconductor chip. (Here, “outer surface” is defined relative the center line of the chips and the center of the gap fills);
re claim 14, Choo (in view of Cho and Jeng) does not explicitly disclose a planar area. However, Jeng illustrates (in a plane of Figure 1B) that a first planar area of the first semiconductor chip is equal to a fourth planar area of the fourth semiconductor chip (i.e., the first chip 132A and the fourth chip 132D are shown to have the same/equal area);
re claim 15, Choo (in view of Cho and Jeng) does not explicitly disclose a second and third chip with smaller planar areas than the first planar area, however, the current claim is deemed because process variation in the dicing of chips ready results in slight variations in chip sizes (i.e., when dicing a wafer into a plurality of chips, there would be slight variations in size at least in an atomic, nanometer, etc. scale). Given this process variation, it would have been obvious to a POSITA to place these smaller dies in the middle of stack such that the bottommost die and the topmost dies in the stack provide an overhang for structural support of the gap fills at the outer surfaces of the middle dies. Furthermore, because a clear meaning of “smaller” (i.e., “substantially smaller”, or a specific metric) has not been defined, minute variations during processing render obvious different sizes of dies within each core die.
re claim 16, Jeng teaches the first semiconductor chip 132A (Fig. 1B) includes a plurality of first through electrodes (Exbibit C above, “first through electrodes”) that electrically connect the plurality of first conductive pads (Exbibit C, “first conductive pads…”) and the plurality of first bonding pads (Exbibit C, “first bonding pads…”),
each of the plurality of second semiconductor chips 132B (Fig. 1B) includes a plurality of second through electrodes (Exbibit C, “second through electrodes”) that electrically connect the plurality of second conductive pads (Exbibit C, “second conductive pads…”) and the plurality of second bonding pads (Exbibit C, “second bonding pads…”), and
each of the plurality of third semiconductor chips includes a plurality of third through electrodes (Exbibit C, “third through electrodes”) that electrically connect the plurality of third conductive pads (Exbibit C, “third conductive pads…”) and the plurality of third bonding pads (Exbibit C, “third bonding pads…”);
re claim 18, Choo discloses the buffer die includes:
a plurality of second substrate pads (See Exhibit B, “second substrate pads”) exposed from the second surface of the buffer die; and a plurality of external connection bumps (See Exhibit B, “external bumps”) provided on the plurality of second substrate pads, respectively; and
re claim 19, Jeng teaches conductive pads made of Copper, Tungsten and other metals, and therefore, it would be obvious to a POSITA to use, for the first to third conductive pads and the first to fourth bonding pads, at least one of Copper (Cu), Aluminum (Al), Tungsten (W), Nickel (Ni), Molybdenum (Mo), Gold (Au), Silver (Ag), Chromium (Cr), Tin (Sn), and Titanium (Ti).
Therefore, claims 12-16, 18 and 19 are rendered obvious by Choo (in view Jeng).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Choo (in view of Jeng and Cho) as applied to Claims 1, and further in view of Bowers (“Thin Quad Die Package (QDP) Development”, Semienengeering.com, Jan 20, 2022).
Regarding claim 8:
Choo (in view of Jeng and Cho) is silent as to a height of the stacked package, Bowers teaches a stacked package of four chips with a height of 200µm or less. Therefore, it would be obvious to a POSITA to incorporate a stack with a height less than 200µm in order to increase compute power while decreasing package size.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Choo (in view of Jeng) as applied to Claims 11, and further in view of Bowers.
Regarding claim 17:
Choo (in view of Jeng) is silent as to a height of the stacked package, Bowers teaches a stacked package of four chips with a height of 200µm or less. Therefore, it would be obvious to a POSITA to incorporate a stack with a height less than 200µm in order to increase compute power while decreasing package size.
Conclusion
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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