DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-14, drawn to a semiconductor structure, classified in CPC H10W90/00.
II. Claims 15-20, drawn to a method of forming a semiconductor structure, classified in CPC H10W80/211.
The inventions are independent or distinct, each from the other because:
Inventions II and I are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case, the product Group I as claimed can be made by another and materially different process. For example, Group I could be made without using a carrier substate material, wherein the alternating stack of insulating layers are formed in their final configuration rather than over a temporary carrier substrate, as is required by the method Group II.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
Group I would not be searched as Group II and would require a search in at least CPC H10W90/00 along with a unique text search. Group II would not be searched as Group I and would require a search in at least CPC H10W80/211 along with a unique text search.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
During a telephone conversation with Leon Radomsky on 06/16/2026 a provisional election was made without traverse to prosecute the invention of Group I, claims 1-14. Affirmation of this election must be made by applicant in replying to this Office action. Claims 15-20 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
The examiner has required restriction between product or apparatus claims and process claims. Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined.
In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104. Thus, to be allowable, the rejoined claims must meet all criteria for patentability including the requirements of 35 U.S.C. 101, 102, 103 and 112. Until all claims to the elected product/apparatus are found allowable, an otherwise proper restriction requirement between product/apparatus claims and process claims may be maintained. Withdrawn process claims that are not commensurate in scope with an allowable product/apparatus claim will not be rejoined. See MPEP § 821.04. Additionally, in order for rejoinder to occur, applicant is advised that the process claims should be amended during prosecution to require the limitations of the product/apparatus claims. Failure to do so may result in no rejoinder. Further, note that the prohibition against double patenting rejections of 35 U.S.C. 121 does not apply where the restriction requirement is withdrawn by the examiner before the patent issues. See MPEP § 804.01.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/08/2024, 02/19/2025, and 04/16/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claim 10 is objected to because of the following informalities:
Claim 10, line 1: “wherein further comprising a…” should (presumably) read --- “further comprising a…
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-7, and 13 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. PG Pub No US2024/0008274A1).
Regarding claim 1, Kim teaches a semiconductor structure [see figs. 2, 3A-3B, 0024-0025], comprising:
an alternating stack of insulating layers (220) fig. 2 [0031] and electrically conductive layers (230) fig. 2 [0039-0040] (formed of metal such as tungsten W [0039-0040]; Tungsten described by [0055 Kim] as electrically conductive metal) that alternate along a vertical direction;
a memory opening (‘channel hole H’ in stack 220, 230 [0034] - filled by CH) fig. 2 [0034, 0031] vertically extending (‘vertically penetrates’ [see abstract]; centers of vertical structures CH aligned in vertical direction [0009, 0038, 0047]) through the alternating stack (220, 230);
a memory opening fill structure (CH) fig. 2 [0033-0034] located in the memory opening (‘channel hole’ H) and comprising a vertical semiconductor channel (240) fig. 3A [0044-0045] and a vertical stack (245) fig. 3a [0044] of memory elements (ME’s; defined based on “portions of the memory material layer 245 located at levels of the electrically conductive layers 230”, in accordance with [0336-0337] instant application specification) (see annotated fig. 3A below); and
a layer stack (210) fig. 3A [0033-0035] of an undoped semiconductor material layer (207) fig. 3A [0035] and a doped (n-doped) [0035] source semiconductor layer (209) fig. 3A [0035], wherein the undoped semiconductor material layer (207) contacts (directly contacts) a bottom end of the vertical semiconductor channel (240) (when considered from the flipped perspective of annotated fig. 3A below – which more closely aligns with the orientation of the claimed invention).
[AltContent: arrow][AltContent: oval][AltContent: arrow][AltContent: arrow][AltContent: textbox (ME’s = memory elements)][AltContent: oval][AltContent: oval][AltContent: arrow][AltContent: rect][AltContent: textbox (HEP20) fig. 2 [0031])][AltContent: arrow][AltContent: oval][AltContent: arrow][AltContent: oval][AltContent: textbox (BP)][AltContent: textbox (TP)][AltContent: arrow][AltContent: arrow][AltContent: textbox (HP1(220) fig. 2 [0031])][AltContent: textbox (HP2)][AltContent: rect][AltContent: rect]
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Annotated fig. 3A of Kim
Regarding claim 2, Kim teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 1. Kim also teaches wherein the undoped semiconductor material layer (207) fig. 3A [0035] comprises a horizontally-extending portion (HEP) [see annotated fig. 3A above] contacting (thermally contacting) a bottom surface of a bottommost insulating layer (bottommost 220 in annotated fig. 3A above) [0031] of the insulating layers (220) fig. 2 [0031] (207 and 203 both formed of thermally-conductive silicon [0033, 0035] and are thermally connected/ in thermal contact with to each other and at least a bottom surface of bottommost 220 [0031] directly contacted to 203 with 207 semiconductor material) and a vertically-extending tubular portion (BP) [see annotated fig. 3A above] contacting a cylindrical surface segment (CH/240 shaped substantially as hollow cylinders [see also fig. 2]) of an inner sidewall of the vertical semiconductor channel (240) fig. 3A [0044-0045].
Regarding claim 5, Kim teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 1. Kim also teaches wherein:
a bottom periphery (BP) [see annotated fig. 3A above] of a contact area between the undoped semiconductor material layer (207) fig. 3A [0035] and the vertical semiconductor channel (240) fig. 3A [0044-0045] is located below a first horizontal plane (HP1) [see annotated fig. 3A above] including a bottom surface of a bottommost electrically conductive layer (ECL1 of 230) fig. 3A [0039] of the electrically conductive layers (230) [0039-0040]; and
a top periphery (TP) [see annotated fig. 3A above] of the contact area is located above a second horizontal plane (HP2) [see annotated fig. 3A above] including a top surface of the bottommost electrically conductive layer (ECL1) (see flipped perspective of annotated fig. 3A of Kim above).
Regarding claim 6, Kim teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 1. Kim also teaches wherein:
the memory opening fill structure (CH) fig. 2 [0033-0034] comprises a dielectric core (247) fig. 3A [0034] (formed of low-k dielectric [0047]) that is laterally surrounded by the vertical semiconductor channel (240) fig. 3A [0044-0045]; and
an entirety of a contact area between the undoped semiconductor material layer (207) fig. 3A [0035] and the dielectric core (247) is located above a horizontal plane (HP2) [see annotated fig. 3A above] including a top surface of a bottommost electrically conductive layer (ECL1 of 230) fig. 3A [0039] of the electrically conductive layers (230) (see perspective of annotated fig. 3A above).
Regarding claim 7, Kim teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 1. Kim also teaches wherein:
the vertical semiconductor channel (240) fig. 3A [0044-0045] has a doping (p-type [0045]) of a first conductivity type (p-type) [0045]; and
the source semiconductor layer (209) fig. 3A [0035] has a doping (n-type doping [0035]) of a second (n-type [0035]) conductivity type that is an opposite of the first conductivity type (p-type [0045]).
Regarding claim 13, Kim teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 1. Kim also teaches wherein:
the vertical semiconductor channel (240) fig. 3A [0045] comprises first conductivity type polysilicon (p-type polysilicon [0045]);
the undoped semiconductor material layer (207) fig. 3A [0035] comprises undoped polysilicon [0035]; and
the doped source semiconductor layer (209) fig. 3A [0035-0036] comprises heavily doped (relatively-high [0036]) second conductivity type polysilicon (n-type polysilicon [0036]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2024/0008274A1), as applied in claim 7 above, in view of Nishikawa (U.S. PG Pub No US2017/0092654A1) and Cui (U.S. PG Pub No US2020/0098780A1).
Regarding claim 8, Kim teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 7. However, Kim does not explicitly disclose wherein:
the undoped semiconductor material layer (207) fig. 3A [0035] comprises atoms of electrical dopants at a net atomic concentration less than 1 x 10^16/cm^3 (numerical concentration range(s) not explicitly recited);
the vertical semiconductor channel (240) fig. 3A [0045] comprises atoms of dopants of the first conductivity type (p-type [0045]) at a first atomic concentration that is less than 3 x 10^16/cm^3 (numerical concentration range(s) not explicitly recited); and
the source semiconductor layer (209) fig. 3A [0035-0036] comprises dopants of the second conductivity type (n-type [0036]) at a second atomic concentration that is greater than 5 x 10^18/cm^3 (numerical concentration range(s) not explicitly recited).
Nishikawa teaches a semiconductor structure [see fig. 14A, 0118] wherein:
the undoped semiconductor material layer (represented by 61) fig. 14A [0098] comprises atoms of electrical dopants at a net atomic concentration less than 1 x 10^16/cm^3 (undoped semiconductor material defined as having atomic concentration less than 1x10^16 atoms/cm^3 [0098, 0116], as opposed to doped semiconductor material having concentration greater than that level [0098]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the “undoped” polysilicon material of Kim’s source structure to explicitly have a dopant concentration below 1x10^16 atoms/cm^3 [0098] in order to limit the dopant concentration of a preferably “undoped” semiconductor layer [0098] according to art recognized guidelines for the atomic concentrations of “undoped” semiconductor material, as evidenced by Nishikawa [0098].
However, Kim in view of Nishikawa does not explicitly disclose wherein:
the vertical semiconductor channel (240) fig. 3A [0045] comprises atoms of dopants of the first conductivity type (p-type [0045]) at a first atomic concentration that is less than 3 x 10^16/cm^3 (numerical concentration range(s) not explicitly recited); and
the source semiconductor layer (209) fig. 3A [0035-0036] comprises dopants of the second conductivity type (n-type [0036]) at a second atomic concentration that is greater than 5 x 10^18/cm^3 (numerical concentration range(s) not explicitly recited).
Cui teaches a semiconductor structure [see fig. 22H, 0200] wherein the vertical semiconductor channel (60) fig. 22H [0163] comprises atoms of dopants of the first conductivity type (first conductivity type [0163]) at a first atomic concentration that is less than 3 x 10^16/cm^3 (may be 1.0x10^14 atoms/cm^3 – 3.0 x 10^17 atoms/cm^3 [0163] – overlapping with the claimed range, see discussion below); and
the source semiconductor layer (112) fig. 22H [0190] comprises dopants of the second conductivity type (second conductivity type [0190]) at a second atomic concentration that is greater than 5 x 10^18/cm^3 (source structure 112 may be doped in range from 5.0x 10^19 atoms/cm^3 – 2.0 x 10^21 atoms/cm^3 [0190] – entirely greater than 5x10^18 atoms/cm^3 as claimed).
While Cui does not explicitly disclose wherein the vertical semiconductor channel comprises atoms of dopants …. at a first atomic concentration that is less than 3 x 10^16/cm^3, Cui discloses that vertical semiconductor channel (60) fig. 22H [0163] may comprise atoms of dopants at a first atomic concentration of 1.0x10^14 atoms/cm^3 – 3.0 x 10^17 atoms/cm^3 [0163]. These ranges overlap. Therefore, in the absence of evidence of criticality for the narrower/lower range recited in the claims, one of ordinary skill in the art would consider Cui [0163] to sufficiently disclose that atomic concentration(s) of less than 3.0x10^16 atoms/cm^3 may be present in the channel [0163] – i.e., the concentration of atoms may range from 1.0x10^10^14 atoms/cm^3 to less than 3.0x10^16 atoms/cm^3 [0163]. (See MPEP 2144.05, I).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the channel [0163] and heavily-doped source structure [0190] of Kim in view of Nishikawa to have the atomic concentration of dopants [0163, 0190] prescribed by Cui in order to explicitly guarantee appropriate dopant and conductivity properties for the channel semiconductor material [0163] and source structure semiconductor material [0190], respectively, according to art recognized guidelines, as evidenced by Cui.
Regarding claim 9, Kim in view of Nishikawa and Cui teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 8. Kim in view of Nishikawa and Cui also teaches wherein the net atomic concentration of the atoms of electrical dopants in the undoped semiconductor material layer (“undoped” semiconductor material has dopant concentration less than 1x10^16 atoms/cm^3 [0098, 0116 Nishikawa]) is less than twice the first atomic concentration (may be less than 3.0x10^16 atoms/cm^3 [0163 Cui] – for example, may be 2.5 x 10^16 atoms/cm^3 [0163 Cui] – which is more than twice an upper limit of 1.0x10^16 atoms/cm^3 [0098 Nishikawa] for undoped material).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2024/0008274A1), as applied in claim 1 above, in view of Kim-II (U.S. PG Pub No US2022/0093629A1).
Regarding claim 10, Kim teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 1. However, Kim does not explicitly disclose further comprising a metallic source contact layer contacting a bottom surface of the source semiconductor layer (209) fig. 3A [0035-0036].
Kim-II teaches a semiconductor structure [see fig. 7, fig. 10 [0055] further comprising a metallic source contact layer (MSC) fig. 10 [0099] (MSC formed of metallic silicide [0099]) contacting (thermally/electrically contacting through conductive MSC [0099] and thermally/electrically conductive CST [0064-0066]) a bottom surface of the source semiconductor layer (SC) fig. 10 [0065].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have disposed conductive contact structures [0099 Kim-II] against and in electrical contact with the semiconductor layers of the source structure [0064-0066, 0099 Kim-II] of the semiconductor structure of Kim in order to form a high-speed current path [0100] through the conductive material of the conductive contact(s) [0099-0100] and source structure semiconductor layers [0064-0066, 0099-0100], thereby improving electric and relatability characteristics of the semiconductor device [0190, 0100], as taught by Kim-II.
Regarding claim 11, Kim in view of Kim-II teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 10. Kim in view of Kim-II (with reference to Kim-II) also teaches wherein the metallic source contact layer (MSC) fig. 10 [0099], the source semiconductor layer (SC) fig. 10 [0065], and the undoped semiconductor material layer (SP) fig. 10 [0066] have vertically coincident (directly bordering, vertically-aligned) sidewalls.
Regarding claim 12, Kim in view of Kim-II teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 11. Kim in view of Kim-II (with reference to Kim-II) also teaches further comprising:
a backside dielectric layer (110 with 55) fig. 10 [0061, 0067, 0095] (may be formed, at least partially, of insulator like low-k dielectric [0061, 0067]) underlying (at least partially underlying) the metallic source contact layer (MSC) fig. 10 [0099]; and
an electrically conductive source contact structure (ME4) fig. 10 [0097-0098] (formed of conductive metal [0098]) vertically extending through the backside dielectric layer (110 with 55) and electrically connected to the metallic source contact layer (MSC) (MSC, ME4 and BM4 are each formed of electrically conductive metal materials [0097-0099, 0107] and are electrically interconnected with one another [0097-0099]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2024/0008274A1), as applied in claim 1 above, in view of Nishida (U.S. PG Pub No US2020/0286875A1).
Regarding claim 14, Kim teaches the semiconductor structure [see figs. 2, 3A-3B, 0024-0025] of claim 1. However, Kim does not explicitly disclose wherein:
the alternating stack (220, 230) fig. 2 [0031, 0039-0040], the memory opening fill structure (CH) fig. 2 [0033-0034], and the source semiconductor layer (209) fig. 3A [0035-0036] are located in a memory die that includes memory-side dielectric material layers embedding memory-side metal interconnect structures and memory-side bonding pads; and
the semiconductor structure further comprises a logic die including a peripheral circuit to the memory die.
Nishida teaches a semiconductor structure [see figs. 24A-24C, Fig. 24F] wherein:
the alternating stack (132, 146, 232, 246) fig. 24F [0288], the memory opening fill structure (58) fig. 24F [0156], and the source semiconductor layer (61 of 310) fig. 24F [0079, 0162-0163] (source regions 61 [0162] formed in semiconductor 310 [0079]) are located in a memory die (1000) fig. 24A [0259] that includes memory-side dielectric material layers (390) fig. 24A [0263] embedding memory-side metal interconnect structures (370) fig. 24A [0280] and memory-side bonding pads (378) fig. 24A [0260]; and
the semiconductor structure [see fig. 24F] further comprises a logic die (900) fig. 24B [0260] including a peripheral circuit [0286-0287] (comprising 942 [0172]) bonded (378/978 bonded [0261]) to the memory die (1000) [see fig. 24C, fig. 24F].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have configured the memory stack components in a memory die [0259] directly connected / bonded to a logic die [0260-0261, 0274] in order to vertically integrate well-connected [0261, 0274] memory storage elements [0286-0287] with logic circuitry to operate the memory elements [0286-0287], as taught by Nishida.
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is objected to as containing allowable subject matter because the prior art of record neither anticipates nor renders obvious the claimed limitation(s) “and the undoped semiconductor material layer further comprises a funnel-shaped portion contacting a tapered end surface of the memory material layer” in the context of claim 3, dependent upon claim 2, dependent upon claim 1. Claim 4 is also objected to as containing allowable subject matter by virtue of its dependency on claim 3.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Baraskar (U.S. PG Pub No US20210375910A1), Lee (U.S. PG Pub No US2022/0068962A1), and Choi (U.S. PG Pub No US2017/0213843A1) teach other examples of source structures beside memory fill structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/26/2026
Prosecution Insights