Prosecution Insights
Last updated: October 26, 2026
Application No. 18/658,562

DISPLAY DEVICE

Non-Final OA §103
Filed
May 08, 2024
Priority
Jun 21, 2023 — RE 10-2023-0079379
Examiner
STARK, JARRETT J
Art Unit
Tech Center
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
914 granted / 1299 resolved
+10.4% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
59 currently pending
Career history
1375
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
62.6%
+22.6% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1299 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Myoung (US 20210159415 A1). CLAIM 1. Myoung teaches a display device comprising: a substrate 210 (FIG. 11, ¶145 disclosing SiO2 substrate); a plurality of pixel electrodes 220 disposed on the substrate 210 and spaced apart from each other at a first interval ( FIG. 11, parallel electrode lines 220 disposed on substrate 210 and spaced apart from each other at a pitch/gap interval; ¶88 disclosing inter-electrode array pitch/spacing up to 100µ); and a plurality of light emitting elements respectively disposed on the plurality of pixel electrodes 220, wherein each of the pixel electrodes 220 has a rectangular shape having a long side and a short side (FIG. 11, pixel electrode lines 220 extending across the substrate having a defined length long side and width short side; ¶69, 110 disclosing rectangular subpixels/electrodes), and a width of each of the light emitting elements 120 is larger than a width of the short side and smaller than the first interval between the pixel electrodes 220 (FIG. 11 illustrates micro light-emitting elements 120 having a width spanning wider than the short side of pixel electrode lines 220 while remaining narrower than the interval gap between adjacent electrode lines 220; ¶71 disclosing element widths/diameters of 10-80µ); and ¶] disclosing array pitch/spacing up to 100µ). Myoung explicitly discloses overlapping dimensional ranges for each structural component, including light emitting element widths/diameters ranging from 1 to 80µ (¶71), pixel electrode/line widths across sub-micron to micrometer dimensions (¶69, 110), and inter-electrode pitch/intervals up to 100µ (¶88). Because the working ranges disclosed in Myoung for element width, electrode line width, and inter-electrode spacing overlap, and are subjectively shown in figure 11, the claimed dimensional relationship (short side width < element width < inter-electrode interval) results from selecting parameter values within those overlapping ranges. Where the prior art discloses overlapping ranges for physical dimensions, establishing a specific relative inequality or conditional relationship among those dimensions represents a matter of routine optimization (In re Aller, 220 F.2d 454, 105 USPQ 233 (CCPA 1955); MPEP § 2144.05). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to select values from within the overlapping ranges taught by Myoung to satisfy the relative inequality (short side width < element width < inter-electrode interval) in order to maximize active light-emitting area over the electrode while maintaining sufficient clearance to prevent bridging or short-circuiting between adjacent lines. CLAIM 2. Myoung teaches a display device of claim 1, wherein each of the light emitting elements comprises a second semiconductor layer an active layer disposed on the second semiconductor layer; and a first semiconductor layer disposed on the active layer, (¶65, 123 disclosing micro light-emitting diode 200 comprising a vertical semiconductor stack of a first semiconductor layer, active layer, and second semiconductor layer); and a width of the first semiconductor layer is larger than the width of the short side and smaller than the first interval between the pixel electrodes 120 (FIG. 11, ¶71, 123 disclosing that the semiconductor layers share the cross-sectional width of the micro-LED element). As set forth in claim 1, because Myoung teaches overlapping dimensional ranges for the semiconductor layers forming the element width (1 to 80µ) and the electrode short side and inter-electrode gap, satisfying the relative width inequality for the first semiconductor layer represents an outcome of routine optimization within those overlapping ranges (MPEP § 2144.05). CLAIM 3. Myoung teaches a display device of claim 2, wherein each of the light emitting elements further comprises a connection electrode 210/230 disposed on the first semiconductor layer and connected to a corresponding one of the pixel electrodes, and a width of the connection electrode is larger than the width of the short side of the one pixel electrode and smaller than the first interval between the pixel electrodes (¶123 disclosing the connection electrode interface spanning across the width of the element). Myoung teaches overlapping dimensional ranges for the micro-LED terminal connection structures and underlying electrode lines. Selecting connection electrode dimensions within these overlapping ranges to meet the claimed conditional inequality would have been obvious to a person having ordinary skill in the art to ensure broad contact coverage and structural balance over the pixel electrode line without shorting adjacent electrodes (MPEP § 2144.05). CLAIM 4. Myoung teaches a display device of claim 1, wherein the width of each of the light emitting elements ranges from 8 μm to 16 μm. Myoung discloses micro light-emitting elements having a width/diameter of 10µm (¶71, 145, 171), as well as a broader range of 1µm to 80µm (¶71). Myoung explicitly disclosed point value of 10 µm falls squarely within the claimed range of 8 µm to 16 µm, and the range taught in Myoung directly encompasses and overlaps the claimed range. Under MPEP § 2144.05, a prior art disclosure that teaches a specific point value (10 µm or a broad range (1 to 80 µm) overlapping a claimed sub-range (8 to 16 µm) establishes a prima facie case of obviousness. Selecting 8 to 16 µm represents routine optimization of known working dimensions within an established, overlapping range, and Applicant has not demonstrated any critical or unexpected results flowing from this specific sub-range (In re Seaborg, 328 F.2d 996, 140 USPQ 662 (CCPA 1964)). CLAIM 5. Myoung teaches a display device of claim 4, wherein a length of the short side of one of the pixel electrodes ranges from 6 μm to 8 μm, a length of the long side of the one pixel electrode ranges from 45 μm to 55 μm, and the first interval ranges from 16 μm to 19 μm. Myoung teaches overlapping working ranges for pixel electrode short side width (sub-micron up to tens of micrometers; paragraphs ¶69], 110), long side length (tens of micrometers; paragraphs ¶69, 110), and inter-electrode pitch/intervals (1 to 100µ; paragraph ¶88). The claimed ranges (6µ short side, 45µ long side, 16-19µ interval) fall squarely within and overlap the broad dimensional ranges disclosed in Myoung. Under MPEP § 2144.05, where the ranges disclosed in the prior art encompass or overlap the claimed ranges, a prima facie case of obviousness is established. Selecting specific numerical limits within these overlapping ranges represents routine optimization of parameters to suit pixel density and aspect ratio requirements (In re Aller, 220 F.2d 454, 105 USPQ 233 (CCPA 1955)). Applicant has provided no evidence of critical or unexpected results across these specific numerical bounds. CLAIM 6. Myoung teaches a display device of claim 5, further comprising a first planarization layer disposed between the pixel electrodes on the substrate (FIG. 11; ¶12], 103, 105 disclosing planarization layers disposed between electrodes/elements over the substrate surface). CLAIM 7. Myoung teaches a display device of claim 6, wherein the one pixel electrode comprises a pixel reflective layer disposed to contact one of the light emitting elements (¶13], 14, 112, 113 disclosing reflective pixel electrode structures/layers disposed beneath and in contact with the light emitting elements). CLAIM 8. Myoung teaches a display device of claim 7, wherein the pixel reflective layer has a reflectivity of 80% or more. Myoung discloses highly reflective pixel layers comprising metallic/reflective materials (e.g., Ag, Al, or distributed Bragg reflectors ¶13], 112). High-reflectivity metals typically exhibit optical reflectivities well above 80% in visible spectrum wavelengths. To the extent that 80% reflectivity is not explicitly quantified, optimizing material composition to achieve a high optical reflectivity of 80% or more is a matter of routine optimization in display device design to maximize light extraction efficiency (In re Aller, 220 F.2d 454, 105 USPQ 233 (CCPA 1955); MPEP § 2144.05). CLAIM 9. Myoung teaches a display device of claim 3, wherein the number of the light emitting elements disposed on the one pixel electrode is three, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second interval, and the second interval ranges from 10 μm to 20 μm. Myoung discloses subpixels/pixel electrodes (PX_sub, PE) having a plurality of light-emitting elements arranged in an array along the electrode line, including 2, 3, or more elements per electrode (FIG. 9, FIG. 11, showing multiple elements 120R, 120G, 120B arranged along subpixel lines; ¶65). Myoung further teaches array spacing/pitch between individual elements along the array ranging from 1µm to 100 µm (¶88]). Disclosing three elements per electrode and an element pitch/spacing range (1 to 100 µm) that directly encompasses and overlaps the claimed sub-range of 10 to 20 µm renders the claimed combination obvious under MPEP § 2144.05. Selecting three elements per electrode spaced at 10-20 µm represents routine parameter optimization to meet brightness and drive redundancy objectives (In re Aller, 220 F.2d 454). CLAIM 10. Myoung teaches a display device of claim 3, wherein the number of the light emitting elements disposed on the one pixel electrode is two, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second interval, and the second interval ranges from 15 μm to 20 μm. As set forth in claim 9, Myoung teaches arrayed pixel lines receiving a plurality of elements (¶65, 88). Arranging two light emitting elements along a single pixel electrode line at an interval within the disclosed 1 to 100 μm range (which overlaps 15-20 μm) is a matter of routine design choice and parameter optimization based on spatial constraints and light output needs (MPEP § 2144.05). CLAIM 11. Myoung teaches a display device of claim 3, wherein the number of light emitting elements disposed on the one pixel electrode is four, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second interval, and the second interval ranges from 10 μm to 15 μm. As set forth in claims 9 and 10, Myoung teaches plurality arrays of micro light-emitting elements along electrode lines (¶65, 88). Providing four light emitting elements along a pixel electrode line at an interval within the overlapping 1 to 100µm disclosed range (overlapping 10-15µm) would have been obvious to a person having ordinary skill in the art to adjust subpixel emission density and redundancy (MPEP § 2144.05). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Myoung (US 20210159415 A1) in view of Iguchi et al. (US 20190267357 A1). CLAIM 12. Myoung teaches the display device of claim 6, but is silent regarding an explicit description of the following structure: a second planarization layer disposed on the first planarization layer and disposed between the light emitting elements; a common electrode disposed on the second planarization layer and the light emitting elements; and a wavelength converter disposed on the common electrode, wherein the wavelength converter comprises a partition wall partitioning emission areas and a non-emission area, a wavelength conversion layer disposed between the partition walls and overlapping the emission areas, a light blocking member disposed on the partition wall, and color filters disposed on the wavelength conversion layer, wherein the light blocking member does not overlap the one pixel electrode. However, Myoung focuses primarily on the layout and relative spacing of micro-LED devices within a display (as addressed regarding claims 1–11) and largely omits conventional features that would inherently be expected in a complete device and observed in cross-sectional views. Iguchi et al. discloses an analogous micro-LED display device to that of Myoung, and further illustrates a conventional cross-sectional view representing what a PHOSITA would expect for such a device. Specifically, Iguchi et al. discloses the missing structure comprising: a second planarization layer 20 disposed on the first planarization layer 50 and disposed between the light emitting elements 15; a common electrode (electrode 56) disposed on the second planarization layer and the light emitting elements 14; and a wavelength converter 21/22/26 disposed on the common electrode. Iguchi et al. further teaches that the wavelength converter comprises a partition wall 20 partitioning emission areas and a non-emission area, a wavelength conversion layer 21/22/23 disposed between the partition walls and overlapping the emission areas, a light blocking member 27 disposed on the partition wall 24 [see Fig. 14 and ¶ 110, 133–149], and color filters disposed on the wavelength conversion layer 21/22/23, wherein the light blocking member 24/27 does not overlap the one pixel electrode [see Iguchi et al., Figs. 10 & 14]. Iguchi et al. notes that such a device may include partition layers between the micro-LEDs, overlying conversion layers, and/or filter layers, and that these partitions may be light blocking, transparent, and/or reflective depending on known, desired performance results. It would have been obvious to a PHOSITA at the time the invention was made to incorporate the partition wall, wavelength conversion layer, color filter, and non-overlapping light-blocking member configuration of Iguchi et al. into the display device of Myoung. A PHOSITA would have been motivated to position the light-blocking member directly over the partition walls without overlapping the pixel electrode to prevent optical cross-talk between adjacent sub-pixels while simultaneously maximizing the aperture ratio and ensuring unhindered light output from the active pixel region. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JARRETT J. STARK Primary Examiner Art Unit 2822 10/7/2026 /JARRETT J STARK/Primary Examiner, Art Unit 2898
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Prosecution Timeline

May 08, 2024
Application Filed
Oct 08, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
81%
With Interview (+11.0%)
2y 8m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1299 resolved cases by this examiner. Grant probability derived from career allowance rate.

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