DETAILED ACTION
Claims 1, 3-10, 12-16 and 18-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 07/21/2026 for application number 18/658,600.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju et al. (US 2012/0230126 A1) in view of Delepaut (US 5,444,358).
Regarding claim 1, Ramaraju teaches a method comprising:
outputting, using a voltage regulator, a regulated output cache voltage to a cache via a cache power rail (“Examples of memories include caches… Voltage regulators may be used to regulate a voltage provided to a memory.” par 0004 and “Memory 100 includes a voltage regulator 153 that regulates the voltage of regulated node 154 [regulated output cache voltage] … Regulated node 154 [cache power rail] is connected to the low voltage terminals of cells 113, 115, 117, and 119.” par 0018 and Figure 1);
producing, by a cache controller, a cache activity signal, based on the cache being accessed pursuant to an operation (“The logical value to be stored in the cell is then controlled by … a memory controller [cache controller] (not shown).” Par 0015 and “the enable signal [cache activity signal] is asserted when memory 100 is in a normal operating mode. In some embodiments, memory 100 can only be written to or read from when transistor 161 is conductive. When the memory is not being accessed, the EN signal is deasserted.” Par 0026) [the memory controller generates the enable signal based on whether the cache is being accessed], the cache controller performing memory control functions for the cache based on the operation (“The desired value is written to cell 119 by the assertion of word line (WL) connected to the cell that makes conductive programming transistors 125 and 137 to couple the complementary bit lines BL1 and BLB1 to the respective storage nodes of the cell (128 and 130) respectively. The logical value to be stored in the cell is then controlled by which one of the two complimentary bit lines (BL1 and BLB1) is driven to a high voltage and which one is driven to a low voltage by a memory controller (not shown).” Par 0015) [the controller drives bit lines to set/manage logical values within the cache cells based on write operation];
controlling, using the cache activity signal from the cache controller, to selectively shunt current from the voltage regulator (“Regulator 153 includes an enabling transistor 161 to disable the leakage current control feature of node 154. When the enable signal EN is asserted at a high voltage level, the NFET transistor 161 is conductive to pull node 154 to system ground.” Par 0025); and
and wherein the cache controller sends the cache activity signal directly to a control input of the transistor switch to turn off the transistor switch and remove the shunt current from the voltage regulator when while the cache is being accessed (“When the enable signal EN is asserted at a high voltage level, the NFET transistor 161 is conductive to pull node 154 to system ground.” Par 0025 and “in other embodiments, memory 100 can be written to and read from when transistor 161 is non-conductive.” Par 0026 and “regulator 301 may include an enablement transistor (not shown) that is similar to enablement transistor 161 in FIG. 1” par 0039 and paragraph 32-33 and “the control terminal for receiving an enable signal,” claim 4 and Figure 2) [the memory controller sends enablement signal to the control terminal of a transistor to make it non-conductive (off) during read/write operations, removing path to ground and preventing shunting current (pull to ground) away from the regulated node while cache is accessed (memory is being read from/written to); the control input of the switch corresponds to the control terminal (gate) of the enablement transistor 161, Fig 1].
However, Ramaraju does not explicitly teach a shunt current circuit coupled between the cache power rail and a ground potential and wherein the shunt current circuit comprises a transistor switch coupled between the cache power rail and a shunt resistor coupled to ground potential.
In the analogous art, Delepaut teaches a shunt current circuit (PSSR, Figure 1) coupled between the cache power rail and a ground potential (“The power supply shunt regulator PSSR includes in more detail a branch connected in parallel to both the load EL and the solar array section SA and includes junction point JP and ground terminal GND the series connection of the shunt switch having the above-mentioned n-channel Field Effect Transistor FET, a degenerative inductor LD and a current sensing resistor CSR.” col. 6, ll. 52-62), and
wherein the shunt current circuit comprises a transistor switch coupled between the cache power rail and a shunt resistor coupled to ground potential (“the power supply shunt regulator PSSR is also connected between the junction point JP and the ground terminal GND … The power supply shunt regulator PSSR includes in more detail a branch connected in parallel to both the load EL and the solar array section SA and includes junction point JP and ground terminal GND the series connection of the shunt switch having the above-mentioned n-channel Field Effect Transistor FET, a degenerative inductor LD and a current sensing resistor CSR.” col. 6, ll. 52-62) [the shunt current circuit (PSSR) has a transistor switch (FET) and a shunt resistor (CSR) connected in series between the power rail (JP) and ground].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju and Delepaut before him before the effective filing date of the claimed invention, to have modified Ramaraju to incorporate the teachings of Delepaut to include a shunt current circuit coupled between the cache power rail and ground and include a transistor switch and shunt resistor to allow the system to limit shunted current to a specific value, ensuring that transitions to the idle state occurs without current overshoots. (Delepaut, columns 10-11)
Claims 10 and 16 correspond to claim 1 and are rejected accordingly.
Regarding claim 3, Ramaraju and Riccio teach the method of claim 1. Ramaraju further teaches further comprises resetting the cache activity signal, by the cache controller, following the cache being accessed, wherein the shunt current circuit provides shunt current from the voltage regulator based on resetting the cache activity signal (“When the enable signal EN is asserted at a high voltage level, the NFET transistor 161 is conductive to pull node 154 to system ground.” par 0025 and “When the memory is not being accessed, the EN signal is deasserted [following an operation] … in other embodiments, memory 100 can be written to and read from when transistor 161 is non-conductive.” Par 0026) [the controller resets the activity signal when the cache is no longer accessed which transitions the shunt transistor to a conductive state to pull the power rail to ground (providing shunt current) while cache is idle].
Claims 4-6, 13, 14, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju and Delepaut in view of Gruber et al. (US 2022/0103142 A1).
Regarding claim 4, Ramaraju and Delepaut teach the method of claim 1. However, Ramaraju and Delepaut do not explicitly teach wherein the voltage regulator further comprises a two-stage on-chip regulator having a first regulator stage receiving a reference voltage at a first input, and the regulated output cache voltage at a second feedback input, and providing its output coupled to a second regulator stage, the second regulator stage receiving the regulated output cache voltage and providing a gate control signal at its output.
In the analogous art, Gruber teaches wherein the voltage regulator further comprises a two-stage on-chip regulator having a first regulator stage receiving a reference voltage at a first input, and the regulated output cache voltage at a second feedback input, and providing its output coupled to a second regulator stage, the second regulator stage receiving the regulated output cache voltage and providing a gate control signal at its output (“The gate terminal of transistor 525 is coupled to the output voltage terminal Vout (the inverting input terminal of the operational amplifier), the gate terminal of transistor 526 is coupled to the reference voltage terminal Vref (the non-inverting input terminal of the operational amplifier)… The second terminal of transistor 524 and the first terminal of transistor 528 are coupled to a first terminal of capacitance CD and to an output terminal of the operational amplifier 520, providing the bias voltage VB. ” Par 0076 and “The LDO/buffered FVF of FIG. 5h further comprises super source follower 530, implementing the buffer (circuit) of the buffered FVF… The gate terminal of transistor 534 is the input terminal of the buffer (circuit) and is coupled to node VX.” Par 0080 and Figure 5G) [the two-stage architecture where Vout and Vref feed into first stage (op amp 520), whose output (Vb) controls the second stage (530/buffer), provides gate drive signal to the main pass transistor].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju, Delepaut and Gruber before him before the effective filing date of the claimed invention, to have modified Ramaraju and Delepaut to incorporate the teachings of Gruber to include a two-stage regulator by adding the feed-forward compensation circuit to increase phase margin of the circuit and thus improve stability of the circuit at higher bandwidths. (Gruber, paragraph 53)
Claims 13 and 19 correspond to claim 4 and are rejected accordingly.
Regarding claim 5, Ramaraju, Delepaut and Gruber teach the method of claim 4. Gruber further teaches wherein the two-stage on-chip regulator comprises an output transistor receiving the gate control signal coupled to its control input, and receiving a reference voltage coupled to its source, and its drain providing the regulated output cache voltage connected to the cache power rail (“A first terminal (the source terminal) of the pass device MP is coupled to the supply voltage of the buffered FVF, the second terminal (the drain terminal) is coupled to output node/terminal Vout and to the first terminal (the source terminal) of the common-gate amplifier transistor MC.” par 0047 and “The gate terminal of the first transistor MP is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit −gmf.” Par 0052) [Mp is the pass device whose gate terminal (control input) receives signal from gate driver; in the context of a pass transistor in a LDO, the supply voltage is the input being regulated down to output voltage, correspondsing to an upstream reference point for the pass device].
Regarding claim 6, Ramaraju, Delepaut and Gruber teach the method of claim 5. Gruber further teaches wherein the output transistor comprises an output p-type field effect transistor (PFET) receiving the gate control signal coupled to its gate, the reference voltage coupled to its source, and its drain providing the regulated output cache voltage connected to the cache power rail (“A first terminal (the source terminal) of the pass device MP is coupled to the supply voltage of the buffered FVF, the second terminal (the drain terminal) is coupled to output node/terminal Vout and to the first terminal (the source terminal) of the common-gate amplifier transistor MC.” par 0047 and “In examples, the first transistor/pass device transistor MP and the second transistor/common-gate amplifier transistor MC are implemented as a p-channel Metal Oxide Semiconductor Field Effect Transistors (p-MOSFET).” Par 0055).
Claims 14 and 20 correspond to claim 6 and are rejected accordingly.
Claims 7-9, 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju and Delepaut in view of Gruber and in further view of Garag et al. (US 2023/0093729 A1).
Regarding claim 7, Ramaraju, Delepaut and Gruber teach the method of claim 6. However, Ramaraju, Delepaut and Gruber do not explicitly teach wherein the shunt current circuit comprises an NFET coupled between the cache power rail and a shunt resistor coupled to ground potential, the NFET receiving the cache activity signal at its gate, and receiving the regulated output cache voltage at its drain and its source coupled to the shunt resistor.
In the analogous art, Garag teaches wherein the shunt current circuit comprises an NFET coupled between the cache power rail and a shunt resistor coupled to ground potential, the NFET receiving the cache activity signal at its gate, and receiving the regulated output cache voltage at its drain and its source coupled to the shunt resistor (“If the output voltage 622 is above the target output voltage, the output of the op amp 613 increases, allowing for increased shunt current to flow through the source of NMOS transistor 616 to the drain of the NMOS transistor 616 to ground 604, decreasing the output voltage 622.” Par 0081 and “wherein an output of the operational amplifier is connected to a gate of a transistor, wherein a source of the transistor is connected to the output voltage of the voltage regulator, wherein a drain of the transistor is connected to a ground.” Par 0103 and “The analog controller will continuously adjust the shunt current through the transistor 616 based on the output voltage 622.” Par 0087) [this shows the NFET (NMOS transistor) controls the shunt current path between the regulated output voltage (cache power rail 622) and ground and its gate is controlled by analog circuitry (which is enabled by memory operation signal); the function of the transistor 616 effectively acts as the controllable resistor in the shunt path to ground].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju, Delepaut, Gruber and Garag before him before the effective filing date of the claimed invention, to have modified Ramaraju, Delepaut and Gruber to incorporate the teachings of Garag to incorporate an NFET to generate less heat in the system and allow for faster switching speeds.
Regarding claim 8, Ramaraju, Delepaut, Gruber and Garag teach the method of claim 7. Ramaraju further teaches wherein the cache activity turns off the NFET to remove the shunt current from the voltage regulator when the cache is being accessed (“When the enable signal EN is asserted at a high voltage level, the NFET transistor 161 is conductive to pull node 154 to system ground.” par 0025 and “in other embodiments, memory 100 can be written to and read from when transistor 161 is non-conductive.” Par 0026) [the NFET is turned off during read/write operations which stops the transistor from pulling the rail to ground, thereby removing the shunt path].
Claim 12 is covered by claims 7 and 8 and is rejected accordingly.
Regarding claim 9, Ramaraju, Delepaut, Gruber and Garag teach the method of claim 7, Garag further teaches further comprises resetting the cache activity signal, by the cache controller, following the cache being accessed, and wherein the cache activity turns on the NFET to provide shunt current from the voltage regulator based on the reset cache activity signal (“In block 1028, the method 1000 checks if the memory operation is complete. If it is not, the method 1000 loops back to block 1012 in FIG. 10 to check whether the input voltage 602 is higher than the next reference voltage. If it is, the method 1000 proceeds to block 1022 in FIG. 10 , in which the controller circuitry 504 disables the voltage regulator 506.” Par 0092 and “The analog controller will continuously adjust the shunt current through the transistor 616 based on the output voltage 622.” Par 0087) [controller 504 checks for memory operation completion (activity signal reset) and manages shunt transistor, regulating shunt current based on output voltage].
Regarding claim 15, Ramaraju, Delepaut and Gruber teach the system of claim 14. Gruber further teaches wherein the output field effect transistor (FET) comprises an output PFET (“In examples, the first transistor/pass device transistor MP and the second transistor/ common-gate amplifier transistor MC are implemented as a p-channel Metal Oxide Semiconductor Field Effect Transistors (p-MOSFET).” Par 0055) [the output transistor Mp is a PFET].
The remainder of clam 15 corresponds to claim 7 and is rejected accordingly.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju and Delepaut in view of Gruber.
Regarding claim 18, Ramaraju and Delepaut teach the on-chip voltage regulator of claim 16. However, Ramaraju and Delepaut do not explicitly teach wherein the switch comprises a field effect transistor (FET) configured to receive the cache activity signal coupled to its gate, and its source and drain coupled between the cache power rail and the shunt resistor.
In the analogous art, Gruber teaches wherein the switch comprises a field effect transistor (FET) configured to receive the cache activity signal coupled to its gate, and its source and drain coupled between the cache power rail and the shunt resistor (“A first terminal (the source terminal) of the pass device MP is coupled to the supply voltage of the buffered FVF, the second terminal (the drain terminal) is coupled to output node/terminal Vout and to the first terminal (the source terminal) of the common-gate amplifier transistor MC.” par 0047 and “In examples, the first transistor/pass device transistor MP and the second transistor/ common-gate amplifier transistor MC are implemented as a p-channel Metal Oxide Semiconductor Field Effect Transistors (p-MOSFET).” Par 0055).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju, Delepaut and Gruber before him before the effective filing date of the claimed invention, to have modified Ramaraju and Delepaut to incorporate the teachings of Gruber to include a FET by adding the feed-forward compensation circuit to increase phase margin of the circuit and thus improve stability of the circuit at higher bandwidths. (Gruber, paragraph 53)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Gupta et al. (US 2013/0093505 A1) teaches regulating a voltage of a SoC that receives a reference signal having a first property that is constant over a range of conditions and a second signal having a second property that is indicative of the operating condition of the SoC. A comparator compares the first and second signals and sends a regulation signal to regulate the voltage near a target voltage greater than a minimum operating voltage.
Riccio et al. (US 2007/0200536 A1) teaches a voltage drop circuit located between input and output terminals, configured to adjust current flow or its limit values to the connected load. The purpose of this is to provide an adaptable, integrated shunt regulator capable of matching current feeding to specific requirements of the load, ensuring overvoltage protection and reliable operation.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
