DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9, 11 and 12 are rejected under 35 U.S.C. 102 as being anticipated by SONG et al. (US PG Pub 2012/0080806, hereinafter Song).
Regarding claim 1, figures 1 and 3 (partially reproduced below) of Song disclose an apparatus, comprising:
a volatile memory (¶ 41);
a first redistribution layer structure (a) coupled. to the volatile memory (¶ 54);
a second redistribution layer structure (b) coupled to the volatile memory and coupled to the first redistribution layer structure at a same node; and
a third redistribution layer structure (c) coupled in series with the first redistribution layer structure.
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Regarding claim 2, figure 3 of Song discloses a plurality of bond pads (210) between the first redistribution layer structure (a) and the third redistribution layer structure (c).
Regarding claim 3, figure 3 of Song discloses the plurality of bond pads (210) are located at an edge.
Regarding claim 4, figures 1 and 3 of Song disclose a die pad (312) coupled to the volatile memory, wherein the volatile memory is coupled to the first redistribution layer structure and the second redistribution layer structure via the die pad (¶ 54).
Regarding claim 5, figure 3 of Song discloses the volatile memory comprises a memory array (would be within the memory chips), and wherein the die pad (312, in the central area) is located in an area along a center region disposed between memory cell array areas of the memory array.
Regarding claim 6, figure 3 of Song discloses a conductive signal line (132) coupled in series with the second redistribution layer structure (b).
Regarding claim 7, figure 3 of Song discloses one or more bond pads (122) between the second redistribution layer structure (b) and the conductive signal line (132).
Regarding claim 9, figure 3 of Song discloses the first redistribution layer structure (a) and the second redistribution layer structure (b) comprise respective first and second portions of a U-shaped structure.
Regarding claim 11, figure 3 of Song discloses the plurality of bond pads (210) are exposed in an opening of a passivation layer (¶ 170).
Regarding claim 12, figure 3 of Song discloses at least one of the first redistribution layer structure, the second redistribution layer structure, or the third redistribution layer structure is disposed in one or more insulating interlayers (170).
Claims 1, 10, 13, 15, 16, 19 and 20 are rejected under 35 U.S.C. 102 as being anticipated by PARK (US PG Pub 2021/0217731, hereinafter Park).
Regarding claim 1, figures 3 and 4 of Park disclose an apparatus, comprising:
a volatile memory (bottom most chip of stack 200L, hereinafter chip1, ¶ 77);
a first redistribution layer structure (within chip1 connected to pad 210) coupled. to the volatile memory;
a second redistribution layer structure (within the second from the bottom chip of stack 200L, hereinafter chip2, connected to its pad 210) coupled to the volatile memory (chip1) and coupled to the first redistribution layer structure at a same node (pad 210 of chip1); and
a third redistribution layer structure (within the third from the bottom chip of stack 200L, hereinafter chip3, connected to its pad 210) coupled in series with the first redistribution layer structure.
Regarding claim 10, figures 3 and 4 of Park disclose second volatile memory (fourth from the bottom chip of stack 200L, hereinafter chip4) coupled to the third redistribution layer structure (of chip3); and
a fourth redistribution layer (within chip4 connected to its pad 210) coupled to the second volatile memory and the third redistribution layer structure at a common node (pad 210 of chip3).
Regarding claim 13, figures 3 and 4 of Park disclose
a first memory device (second from the bottom chip of stack 200L, hereinafter chip2, ¶ 77);
a second memory device (fourth from the bottom chip of stack 200L, hereinafter chip4);
a first redistribution layer structure (within bottom most chip of stack 200L, hereinafter chip1 connected to pad 210) coupled to the first memory device at a first node (pad 210 of chip2);
a second redistribution layer structure (within the third from the bottom chip of stack 200L, hereinafter chip3, connected to its pad 210) coupled to the first memory device at the first node (pad 210 of chip2); and
a third redistribution layer structure (within chip2, connected to its pad 210) coupled to the second memory device at a second node (pad 210 of chip 4) and coupled in series with the second redistribution layer structure.
Regarding claim 15, figures 3 and 4 of Park disclose a fourth redistribution layer structure (within chip4, connected to its pad 210) coupled to the second memory device (chip4) at the second node (pad 210 of chip4).
Regarding claim 16, figure 3 of Park disclose a plurality of bond pads (210) located at an edge.
Regarding claim 19, figures 3 and 4 of Park disclose a first die pad (210) coupled to the first memory device (chip2), wherein the first memory device is coupled to the first redistribution layer structure (within chip1) and the second redistribution layer structure (within chip3) via the first die pad; and
a second die pad (210) coupled to the second memory device (chip4), wherein the second memory device is coupled to the third redistribution layer structure (within chip2) via the second die pad.
Regarding claim 20, figure 3 of Park disclose the first die pad (210 in the central area) is located within a center region between memory cell array areas of the first memory device (chip2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Song.
Regarding claim 8, Song does not explicitly disclose a register clock driver circuit coupled to the conductive signal line.
However, register clock driver circuits are well known in the art to be part of memory devices and it would have been obvious to include one coupled to the conductive signal line for form a functioning memory device.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Lee et al. (US Pat 11,222,872, hereinafter Lee).
Regarding claims 17 and 18, Park does not explicitly disclose the plurality of bond pads are exposed in an opening of a passivation layer, wherein at least one of the first redistribution layer structure, the second redistribution layer structure, or the third redistribution layer structure is disposed in one or more insulating interlayers.
In the same field of endeavor, figure 1B of Lee discloses a redistribution structure includes a bond pad (123A) exposed in an opening of a passivation layer (125), wherein the redistribution layer structure is disposed in one or more insulating interlayers (121).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the distribution layers and bond pads with the claimed structure arrangement as taught by Lee for the purpose of providing input/output signals to/from each of the stacked die.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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