DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 is objected to because of the following informalities: " is are" on line 5 should be "is". Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, and 9-10 are rejected under U.S.C. 103 as being unpatentable over Lin et al.; US 2024/0395847 A1; 05/2023 in view of Nishida; US 2026/0164827 A1; 05/2024 and Asozu; US 2023/0301124 A1; 03/2023
Claim 1: Lin discloses an organic photodiode ( Fig. 3 photodiodes 212; [0034] are organic photodiodes ), comprising: a device ( Fig. 3 optoelectronic device 300 ), which is formed in a substrate ( Fig. 3 substrate 302 ); an interconnect structure ( Fig. 3 interconnect structure 310a ), which is formed on the device ( Fig. 3 #300 ) and is connected to the device ( as shown in Fig. 3 ); a bottom electrode ( Fig. 2B conductive material 218; [0035] e.g. a bottom electrode layer ), which is formed on the interconnect structure ( Fig 3 #310a ), and is connected to a taper plate ( Fig. 3 metallization layers 312a ) of the interconnect structure ( Fig. 3 #310a )
Lin does not appear to disclose the bottom electrode is completely formed within an upper surface of the taper plate, and wherein a contact area between the bottom electrode and the taper plate is of a same order of magnitude as a pixel size, while the upper surface of the taper plate exceeds the pixel size; and an organic layer, which is formed on the bottom electrode, and is connected to the bottom electrode.
Nishida discloses the bottom electrode ( Fig. 18A: gate electrode 106 ) is completely formed within an upper surface of the taper plate ( [0178] The first conductive pad 108a is disposed within a window part surrounded by the side wall spacer in the side wall of the gate electrode 106 of each of the four transfer transistors 104a ), and wherein a contact area between the bottom electrode ( Fig. 18A #106 ) and the taper plate ( the window part as discussed above ) is of a same order of magnitude as a pixel size( Fig. 18A first pixel block 16a ), while the upper surface of the taper plate ( as shown in Fig. 19 upper surface in the area of 113a ) exceeds the pixel size ( as shown in Fig. 19 ).
Nishida does not appear to disclose an organic layer, which is formed on the bottom electrode, and is connected to the bottom electrode.
However, Asozu teaches an organic layer ( Fig. 2 organic layer 132 ), which is formed on the bottom electrode ( Fig. 2 bottom electrode 134 ), and is connected to the bottom electrode ( Fig. 2 #134 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Asozu with Lin and Nishida to implement an organic layer, which is formed on the bottom electrode, and is connected to the bottom electrode because this approach enhances photocurrent, reduces dark current, improves stability and device uniformity.
Claim 2: Lin, Nishida, and Asozu disclose the organic photodiode of claim 1 ( as discussed above ).
Lin does not appear to disclose the taper plate is connected to a top conduction plug of the interconnect structure, wherein the top conduction plug is connected to a top metal layer of the interconnect structure, and the taper plate has a lower surface opposite to the upper surface, wherein the upper surface is connected to the bottom electrode and the bottom electrode is located within a vertical projection region of the upper surface, wherein the lower surface is connected to the top conduction plug.
However, Nishida teaches the taper plate ( Fig. 6 aperture ab, ag, and ar ) is connected to a top conduction plug ( Fig. 6 metal layer 111 ) of the interconnect structure ( Fig. 6 110 connects the metal layer to the conduction plug ), wherein the top conduction plug ( Fig. 6 contacts 144 ) is connected to a top metal layer ( Fig. 6 metal layer 111 ) of the interconnect structure ( as shown in Fig. 6 ), and the taper plate ( Fig. 6 aperture ab, ag, and ar ) has a lower surface opposite to the upper surface ( as shown in Fig. 6 ), wherein the upper surface is connected to the bottom electrode ( as shown in Fig. 12 ) and the bottom electrode ( Fig. 6 electrodes 145 ) is located within a vertical projection region of the upper surface ( as shown in Fig. 6 and further in Fig. 12 ), wherein the lower surface is connected to the top conduction plug ( as shown in Fig. 12 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Asozu with Lin and Nishida to implement the taper plate is connected to a top conduction plug of the interconnect structure, wherein the top conduction plug is connected to a top metal layer of the interconnect structure, and the taper plate has a lower surface opposite to the upper surface, wherein the upper surface is connected to the bottom electrode and the bottom electrode is located within a vertical projection region of the upper surface, wherein the lower surface is connected to the top conduction plug because this approach ensures robust electrical contact, minimizes interface defects, aligns the photoactive bottom electrode with the IC metal layers, and supports high-performance integration for imaging or sensing applications.
Claim 4: Lin, Nishida, and Asozu disclose the organic photodiode of claim 1 ( as discussed above ).
Neither Lin nor Nishida appear to disclose a material of the bottom electrode includes at least one of the following: titanium nitride, titanium, aluminum, tantalum nitride, tantalum, chromium, silver, and gold.
However, Asozu teaches a material of the bottom electrode includes at least one of the following: titanium nitride, titanium, aluminum, tantalum nitride, tantalum, chromium, silver, and gold ( [0031] The bottom electrode 134 includes a conductive oxide that is transparent to visible light, such as a mixed oxide of indium and tin (ITO) or a mixed oxide of indium and zinc (IZO), a metal such as silver or aluminum, or an alloy of these metals ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Asozu with Lin and Nishida to implement a material of the bottom electrode includes at least one of the following: titanium nitride, titanium, aluminum, tantalum nitride, tantalum, chromium, silver, and gold because these elements are incorporated to engineer the interfacial energy levels, morphology, and carrier selectivity which are essential to achieve high-performance organic photodiodes.
Claim 5: Lin, Nishida, and Asozu disclose the organic photodiode of claim 1 ( as discussed above ).
Neither Lin nor Asozu appear to disclose a readout circuit is additionally formed in the substrate, wherein the readout circuit includes at least one semiconductor device and a readout interconnect structure, and the semiconductor device is electrically connected to the readout interconnect structure, and the readout circuit is coupled to the organic photodiode for reading out a photoelectric signal generated by the organic photodiode.
However, Nishida teaches a readout circuit ( Fig. 3 readout circuit 15 ) is additionally formed in the substrate ( Fig. 7 substrate 20 ), wherein the readout circuit ( Fig. 3 #15 ) includes at least one semiconductor device ( Fig. 3: RST, AMP, and SEL ) and a readout interconnect structure ( as shown in Fig. 3 ), and the semiconductor device ( Fig. 3: RST, AMP, and SEL ) is electrically connected to the readout interconnect structure ( as shown in Fig. 3 ), and the readout circuit ( Fig. 3 #15) is coupled to the organic photodiode ( Fig. 3: PD ) for reading out a photoelectric signal generated by the organic photodiode ( [0063] The readout circuit 15 illustrated in FIG. 3 reads out the signal charge held in the charge holding region FD and outputs a pixel signal based on this signal charge ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Asozu with Lin and Nishida to implement a readout circuit is additionally formed in the substrate, wherein the readout circuit includes at least one semiconductor device and a readout interconnect structure, and the semiconductor device is electrically connected to the readout interconnect structure, and the readout circuit is coupled to the organic photodiode for reading out a photoelectric signal generated by the organic photodiode because this approach ensures effective signal extraction, noise reduction, and system-level efficiency.
Claim 6: Lin discloses a manufacturing method of an organic photodiode, comprising: first, forming a device ( Figs. 4A -4O forming the electronic device of Fig. 3 ) in a substrate ( Fig. 4A substrate 302 ); then, forming an interconnect structure ( Fig. 4C interconnect structures 310a ) on the device ( Fig. 4C #400 ) and connected to the device ( as shown in Fig. 4C ); then, forming a bottom electrode ( Fig. 4D conductive material 218 (e.g., a bottom electrode layer) is formed ) on the interconnect structure ( Fig. 4D #310a ) connected to a taper plate ( Fig. 4D #312a ) of the interconnect structure ( Fig. 4D #310a ).
Lin does not appear to disclose the bottom electrode is completely formed within an upper surface of the taper plate, and wherein a contact area between the bottom electrode and the taper plate is of a same order of magnitude as a pixel size, while the upper surface of the taper plate exceeds the pixel size; and then, forming an organic layer on and connected to the bottom electrode.
Nishida discloses the bottom electrode ( Fig. 18A: gate electrode 106 ) is completely formed within an upper surface of the taper plate ( [0178] The first conductive pad 108a is disposed within a window part surrounded by the side wall spacer in the side wall of the gate electrode 106 of each of the four transfer transistors 104a ), and wherein a contact area between the bottom electrode ( Fig. 18A #106 ) and the taper plate ( the window part as discussed above ) is of a same order of magnitude as a pixel size ( Fig. 18A first pixel block 16a ), while the upper surface of the taper plate ( as shown in Fig. 19 upper surface in the area of 113a ) exceeds the pixel size ( as shown in Fig. 19 ).
Nishida does not appear to disclose forming an organic layer on and connected to the bottom electrode.
However, Asozu teaches forming an organic layer ( Fig. 2 organic layer 132 ) on and connected to the bottom electrode ( Fig. 2 bottom electrode 134 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Asozu with Lin and Nishida to implement forming an organic layer on and connected to the bottom electrode because this approach ensures efficient, selective, and stable charge collection.
Claim 7: Lin, Nishida, and Asozu disclose the manufacturing method of claim 6 ( as discussed above ).
Neither Lin nor Asozu appear to disclose the taper plate is connected to a top conduction plug of the interconnect structure, wherein the top conduction plug is connected to a top metal layer of the interconnect structure, and the taper plate has a lower surface opposite to the upper surface, wherein the upper surface is connected to the bottom electrode and the bottom electrode is located within a vertical projection region of the upper surface, wherein the lower surface is connected to the top conduction plug.
However, Nishida teaches the taper plate ( Fig. 6 aperture ab, ag, and ar ) is connected to a top conduction plug ( Fig. 6 metal layer 111 ) of the interconnect structure ( Fig. 6 110 connects the metal layer to the conduction plug ), wherein the top conduction plug ( Fig. 6 contacts 144 ) is connected to a top metal layer ( Fig. 6 metal layer 111 ) of the interconnect structure ( as shown in Fig. 6 ), and the taper plate ( Fig. 6 aperture ab, ag, and ar ) has a lower surface opposite to the upper surface ( as shown in Fig. 6 ), wherein the upper surface is connected to the bottom electrode ( as shown in Fig. 12 ) and the bottom electrode ( Fig. 6 electrodes 145 ) is located within a vertical projection region of the upper surface ( as shown in Fig. 6 and further in Fig. 12 ), wherein the lower surface is connected to the top conduction plug ( as shown in Fig. 12 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Asozu with Lin and Nishida to implement the taper plate is connected to a top conduction plug of the interconnect structure, wherein the top conduction plug is connected to a top metal layer of the interconnect structure, and the taper plate has a lower surface opposite to the upper surface, wherein the upper surface is connected to the bottom electrode and the bottom electrode is located within a vertical projection region of the upper surface, wherein the lower surface is connected to the top conduction plug because this approach ensures robust electrical contact, minimizes interface defects, aligns the photoactive bottom electrode with the IC metal layers, and supports high-performance integration for imaging or sensing applications.
Claim 9: Lin, Nishida, and Asozu disclose the manufacturing method of claim 6 ( as discussed above ).
Neither Lin nor Nishida appear to disclose a material of the bottom electrode includes at least one of the following: titanium nitride, titanium, aluminum, tantalum nitride, tantalum, chromium, silver, and gold.
However, Asozu teaches a material of the bottom electrode includes at least one of the following: titanium nitride, titanium, aluminum, tantalum nitride, tantalum, chromium, silver, and gold ( [0031] The bottom electrode 134 includes a conductive oxide that is transparent to visible light, such as a mixed oxide of indium and tin (ITO) or a mixed oxide of indium and zinc (IZO), a metal such as silver or aluminum, or an alloy of these metals ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Asozu with Lin and Nishida to implement a material of the bottom electrode includes at least one of the following: titanium nitride, titanium, aluminum, tantalum nitride, tantalum, chromium, silver, and gold because these elements are incorporated to engineer the interfacial energy levels, morphology, and carrier selectivity which are essential to achieve high-performance organic photodiodes.
Claim 10: Lin, Nishida, and Asozu disclose the manufacturing method of claim 6 ( as discussed above ).
Neither Lin nor Asozu appear to disclose forming a readout circuit is additionally in the substrate, wherein the readout circuit includes at least one semiconductor device and a readout interconnect structure, and the semiconductor device is electrically connected to the readout interconnect structure, and the readout circuit is coupled to the organic photodiode for reading out a photoelectric signal generated by the organic photodiode.
However, Nishida teaches a readout circuit ( Fig. 3 readout circuit 15 ) is additionally formed in the substrate ( Fig. 7 substrate 20 ), wherein the readout circuit ( Fig. 3 #15 ) includes at least one semiconductor device ( Fig. 3: RST, AMP, and SEL ) and a readout interconnect structure ( as shown in Fig. 3 ), and the semiconductor device ( Fig. 3: RST, AMP, and SEL ) is electrically connected to the readout interconnect structure ( as shown in Fig. 3 ), and the readout circuit ( Fig. 3 #15) is coupled to the organic photodiode ( Fig. 3: PD ) for reading out a photoelectric signal generated by the organic photodiode ( [0063] The readout circuit 15 illustrated in FIG. 3 reads out the signal charge held in the charge holding region FD and outputs a pixel signal based on this signal charge ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Asozu with Lin and Nishida to implement forming a readout circuit is additionally in the substrate, wherein the readout circuit includes at least one semiconductor device and a readout interconnect structure, and the semiconductor device is electrically connected to the readout interconnect structure, and the readout circuit is coupled to the organic photodiode for reading out a photoelectric signal generated by the organic photodiode because this approach ensures effective signal extraction, noise reduction, and system-level efficiency.
Claims 3 and 8 are rejected under U.S.C. 103 as being unpatentable over Lin et al.; US 2024/0395847 A1; 05/2023 in view of Nishida; US 2026/0164827 A1; 05/2024 and Asozu; US 2023/0301124 A1; 03/2023 as it relates to claim 2 above and further in view of Kurosaki et al.; US 2026/0107505 A1; 11/2023
Claim 3: Lin, Nishida, and Asozu disclose the organic photodiode of claim 2 ( as discussed above ).
Neither Lin nor Nishida nor Asozu appear to disclose an angle between a taper sidewall of the taper plate and a normal to the lower surface ranges from 0 degrees to 45 degrees.
However, Kurosaki teaches an angle between a taper sidewall of the taper plate and a normal to the lower surface ranges from 0 degrees to 45 degrees ( [0069] the tapered shape preferably includes a region where the angle formed by the inclined side surface and the substrate surface or the formation surface (such an angle is also referred to as a taper angle ) is greater than 0° and less than 90° ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kurosaki with Lin, Nishida, and Asozu to implement an angle between a taper sidewall of the taper plate and a normal to the lower surface ranges from 0 degrees to 45 degrees because this range of angles is typical to ensure optical efficiency and electrical performance.
Claim 8: Lin, Nishida, and Asozu disclose the organic photodiode of claim 7 ( as discussed above ).
Neither Lin nor Nishida nor Asozu appear to disclose an angle between a taper sidewall of the taper plate and a normal to the lower surface ranges from 0 degrees to 45 degrees.
However, Kurosaki teaches an angle between a taper sidewall of the taper plate and a normal to the lower surface ranges from 0 degrees to 45 degrees ( [0069] the tapered shape preferably includes a region where the angle formed by the inclined side surface and the substrate surface or the formation surface (such an angle is also referred to as a taper angle ) is greater than 0° and less than 90° ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kurosaki with Lin, Nishida, and Asozu to implement an angle between a taper sidewall of the taper plate and a normal to the lower surface ranges from 0 degrees to 45 degrees because this range of angles is typical to ensure optical efficiency and electrical performance.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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