DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/9/2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lane et al. (US 20080277765 A1, IDS) in view of Parekh (US 20210398847 A1).
Re Claim 1 Lane teaches a semiconductor device (FIG. 7B) comprising:
a lower structure (14B and 12B) [0005];
a plurality of conductive wirings (42 and 44) [0089] on the lower structure (14B and 12B);
an interlayer insulating layer (31) [0089] on the lower structure (14B and 12B) and on side surfaces of the plurality of conductive wirings (42 and 44);
a protective insulating layer (30) [0090] on the interlayer insulating layer (31) and the plurality of conductive wirings (42 and 44); and
an upper insulating structure (140) [0083],
wherein the upper insulating structure (140) includes an upper interlayer (top part of 140) portion on the protective insulating layer (30), and an extension portion (62B) [0099] extending from the upper interlayer portion (top part of 140), penetrating through the protective insulating layer (30), the interlayer insulating layer (31), and extending into the lower structure (14B and 12B, FIG. 7B).
Lane does not teach the extension portion penetrating through a first conductive wiring among the plurality of conductive wirings.
Parekh teaches the extension portion (260 between 256) [0087] penetrating through a first conductive wiring (256) [0084] among the plurality of conductive wirings (FIG. 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Parekh into the structure of Lane since Parekh teaches a semiconductor structure with insulators penetrating metal layers.
The ordinary artisan would have been motivated to modify Parekh in combination with Lane in the above manner for the motivation of optimally integrating an insulating layer through a metal layer to increase the level of integration of features within a microelectronic device. [0003] states, “Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features.”
Re Claim 2 Lane in view of Parekh teaches the semiconductor device of claim 1, wherein the first conductive wiring (Parekh, 256) is divided into a first wiring portion (256 on left) and a second wiring portion (256 on right) spaced apart from each other by the extension portion (260 between 256, FIG. 7).
Re Claim 11 Lane in view of Parekh teaches the semiconductor device of claim 1, wherein a lower end of the first extension portion (Lane, 62B) is located at a level lower than a level of a lower end of the interlayer insulating layer (31, FIG. 7B).
Re Claim 12 Lane in view of Parekh teaches the semiconductor device of claim 1,
wherein the protective insulating layer (Lane, 30, [0089] “hard mask material such as N-BLoK”) includes a material different from a material of the interlayer insulating layer (31 comprises pSiCOH, [0089]), and
wherein the material of the interlayer insulating layer (31) contains a low-κ dielectric material [0089].
Claims 3, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lane et al. (US 20080277765 A1, IDS) in view of Parekh (US 20210398847 A1) as applied to claim 1 above, and further in view of Chen (US 20230155001 A1).
Re Claim 3 Lane in view of Parekh teaches the semiconductor device of claim 1, but does not teach each of the plurality of conductive wirings includes a barrier layer and a wiring layer on the barrier layer.
Chen teaches each of the plurality of conductive wirings (128 and 130) [0051] includes a barrier layer (128) and a wiring layer (130) on the barrier layer (FIG. 20).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen into the structure of Lane in view of Parekh since Chen teaches a semiconductor structure with a metal wiring layer over a barrier liner.
The ordinary artisan would have been motivated to modify Chen in combination with Lane in view of Parekh in the above manner for the motivation of optimally integrating the conductive wiring to reduce contact resistance values of the device. [0008] states, “By forming upper source/drain contact plugs and their overlaying metal lines (referred to as M0 metal lines hereinafter) as dual-damascene structures, the interface therebetween are removed, and contact resistance values are reduced.”
Re Claim 4 Lane in view of Parekh and Chen teaches the semiconductor device of claim 3,
wherein the barrier layer (Chen, 128) includes metal nitride [0051], and
wherein the wiring layer (130) contains ruthenium (Ru) [0051].
Re Claim 6 Lane in view of Parekh and Chen teaches an upper conductive structure (Chen, 120) [0053] penetrating through the upper interlayer portion (102) [0044] and the protective insulating layer (88) [0037] and electrically connected to one conductive wiring (84 over 68) [0034] of the plurality of conductive wirings (84 and 86 over 68, FIG. 20).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lane et al. (US 20080277765 A1, IDS) in view of Parekh (US 20210398847 A1) as applied to claim 1 above, and further in view of Yang et al. (US 20210233843 A1).
Re Claim 5 Lane in view of Parekh teaches the semiconductor device of claim 1,
wherein the plurality of conductive wirings (Lane, 42 and 44) extend in a first direction (in and out of page, FIG. 5A is cross section of FIG. 4 [0064]) and are spaced apart in a second direction (left to right in FIG. 5A), intersecting the first direction (FIG. 4 and 5A), and
Lane in view of Uzoh does not teach a minimum distance between the plurality of conductive wirings in the second direction is 24 nm or less.
Yang [0033] states, “…each via of the at least one set of vias is spaced apart from a nearest neighboring via by a distance of from 15 nm to 60 nm.”
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yang into the structure of Lane in view of Uzoh since Yang teaches a semiconductor structure.
The ordinary artisan would have been motivated to modify Yang in combination with Lane in view of Uzoh in the above manner for the motivation of reaching ideal distance between the plurality of conductive wirings. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal minimum distance for conductive wiring spacing.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lane et al. (US 20080277765 A1, IDS) in view of Parekh (US 20210398847 A1) and Chen (US 20230155001 A1) as applied to claims 1 and 6 above, and further in view of Uzoh et al. (US 20200126861 A1, IDS).
Re Claim 7 Lane in view of Parekh and Chen teaches the semiconductor device of claim 6,
wherein each of the plurality of conductive wirings (Chen, 84 and 86 over 68) includes a first barrier layer (68) [0034] and a first wiring layer (84 and 86) on the first barrier layer (68),
wherein the first barrier layers (68) include a first conductive material ([0034] teaches 68 is a metal layer),
wherein the first wiring layers (84 and 86) include a second conductive material ([0036] teaches 84 and 86 may include comprise tungsten, cobalt, or aluminum), different from the first conductive material (68 metal not explicitly taught, but options are provided for 84 and 86, so one can choose an alternative material).
Lane in view of Parekh and Chen does not teach the extension portion of the upper insulating structure contacts side surfaces of the first barrier layers and side surfaces of the first wiring layers.
Uzoh teaches the extension portion (410) of the upper insulating structure (410, FIG. 4G and 4H) contacts side surfaces of the first barrier layers (206) and side surfaces of the first wiring layers (204, 204 and 410 are in mechanical contact).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Uzoh into the structure of Lane in view of Parekh and Chen since Uzoh teaches a semiconductor structure.
The ordinary artisan would have been motivated to modify Uzoh in combination with Lane in view of Parekh and Chen in the above manner for the motivation of optimally integrating an insulating layer through a metal layer to allow for an optimal structure to be handled during fabrication to minimize costs. [0003] states, “Thin wafer handling in 2.5D and 3D technologies adds cost and complexity in assembly. In particular, wafer bow and cracking of thin wafers, including the interposer, can cause great difficulty during assembly.”
Re Claim 9 Lane in view of Parekh and Chen and Uzoh teaches the semiconductor device of claim 7,
wherein the upper conductive structure (Chen, 120) includes a second barrier layer (128) [0051] and a second wiring layer (130) on the second barrier layer (128), and
wherein the second barrier layer (128) covers a side surface and a lower surface of the second wiring layer (130).
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lane et al. (US 20080277765 A1, IDS) in view of Parekh (US 20210398847 A1) and Chen (US 20230155001 A1) and Uzoh et al. (US 20200126861 A1, IDS) as applied to claims 1 and 6 and 7 above, and further in view of Narkeviciute et al. (WO 2021262527 A1).
Re Claim 8 Lane in view of Parekh and Chen and Uzoh teaches the semiconductor device of claim 7, but does not teach the second conductive material includes ruthenium (Ru).
Narkeviciute teaches the second conductive material (920 A & B, page 37 last par) includes ruthenium (Ru) (FIG. 9).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Narkeviciute into the structure of Lane in view of Parekh and Chen and Uzoh since Narkeviciute teaches an interconnection structure.
The ordinary artisan would have been motivated to modify Narkeviciute in combination with Lane in view of Parekh and Chen and Uzoh in the above manner for the motivation of using ruthenium as the second conductive material to optimize the current in the device as ruthenium is a known transition metal that is temperature sensitive (page 8 par 3).
Re Claim 10 Lane in view of Parekh and Chen and Uzoh and Narkeviciute teaches the semiconductor device of claim 9, wherein the second wiring layer (Narkeviciute, 960 and 970) [0144] includes a conductive material (use copper), different from the second conductive material (920 A & B contain ruthenium).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lane et al. (US 20080277765 A1, IDS) in view of Parekh (US 20210398847 A1) as applied to claim 1 above, and further in view of Lin et al. (US 20230268386 A1).
Re Claim 13 Lane in view of Parekh teaches the semiconductor device of claim 1, but does not teach:
an etch stop layer between the lower structure and the interlayer insulating layer.
Lin teaches an etch stop layer (94) between the lower structure (FIG. 21B, 30 is source/drain [0052] and lower structure) and the interlayer insulating layer (93) [0055].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin into the structure of Lane in view of Parekh since Lin teaches a gate all around device with an etch stop layer.
The ordinary artisan would have been motivated to modify Chen in combination with Lane in view of Parekh in the above manner for the motivation of optimally integrating an etch stop layer to build a device that functions at a peak level and is still as small as possible. [0001] states, “However, due to miniaturization of IC devices, isolation between components in the IC devices, which affects structure stability, capacitance impact, and current leakage, becomes an issue that must be addressed to improve device stability.”
Claims 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lane et al. (US 20080277765 A1, IDS) in view of Uzoh et al. (US 20200126861 A1, IDS) and Parekh (US 20210398847 A1).
Re Claim 14 Lane teaches a semiconductor device (FIG. 5A) comprising:
a lower structure (14B) [0005];
a conductive wiring (42) [0089] on the lower structure (14B);
an interlayer insulating layer (31) [0089] on the lower structure (14B) and disposed on a side surface of the conductive wiring (42); and
an upper insulating structure (30) [0089].
Lane does not teach the upper insulating structure includes an upper interlayer portion on the interlayer insulating layer, and an extension portion extending from the upper interlayer portion, penetrating through the interlayer insulating layer and dividing the conductive wiring into a first wiring portion and a second wiring portion spaced apart from each other.
Uzoh teaches the upper insulating structure (410) [0030] includes an upper interlayer portion (part of 410 directly above 404 in FIG. 4G) on the interlayer insulating layer (202) [0018], and an extension portion (410 portions that extend into 402 in FIG. 4G) extending from the upper interlayer portion (410 directly above 404), penetrating through the interlayer insulating layer (202) and dividing the conductive wiring into a first wiring portion (204, [0018], left of both 408 regions in FIG. 4G) and a second wiring portion (204 between 408 portions in FIG. 4G) spaced apart from each other (FIG. 4G).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Uzoh into the structure of Lane since Uzoh teaches a semiconductor structure.
The ordinary artisan would have been motivated to modify Uzoh in combination with Lane in the above manner for the motivation of optimally integrating an insulating layer through a metal layer to allow for an optimal structure to be handled during fabrication to minimize costs. [0003] states, “Thin wafer handling in 2.5D and 3D technologies adds cost and complexity in assembly. In particular, wafer bow and cracking of thin wafers, including the interposer, can cause great difficulty during assembly.”
Lane in view of Uzoh does not teach the extension portion penetrating through the conductive wiring.
Parekh teaches extension portion (260 between 256) [0087] penetrating through the conductive wiring (256, FIG. 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Parekh into the structure of Lane in view of Uzoh since Parekh teaches a semiconductor structure with insulators penetrating metal layers.
The ordinary artisan would have been motivated to modify Parekh in combination with Lane in view of Uzoh in the above manner for the motivation of optimally integrating an insulating layer through a metal layer to increase the level of integration of features within a microelectronic device. [0003] states, “Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features.”
Re Claim 18 Lane in view of Uzoh and Parekh teaches the semiconductor device of claim 14, wherein the first wiring portion (Uzoh, 204 to left of both 408 regions in FIG. 4G) and the second wiring portion (204 between 408 portions in FIG. 4G) respectively have a bar shape or a line shape extending in a first direction (vertical) , wherein a width of each of the first and second wiring portions (204) in a second direction (horizontal) is less than a width of the extension portion (410 portions that extend into 402 in FIG. 4G) in the second direction (horizontal), and wherein the second direction (horizontal) is perpendicular to the first direction (vertical).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lane et al. (US 20080277765 A1, IDS) in view of Uzoh et al. (US 20200126861 A1, IDS) and Parekh (US 20210398847 A1) as applied to claim 14 above, and further in view of Narkeviciute et al. (WO 2021262527 A1).
Re Claim 15 Lane in view of Uzoh and Parekh teaches the semiconductor device of claim 14, but does not teach the first and second wiring portions respectively include a first barrier layer and a first wiring layer on the first barrier layer,
wherein the first barrier layers include a first conductive material,
wherein the first wiring layers include a second conductive material, different from the first conductive material, and
wherein the extension portion of the upper insulating structure contacts side surfaces of the first barrier layers and side surfaces of the first wiring layers.
Narkeviciute teaches the first (920A & 922, page 37 par 3) and second (290B & 922) wiring portions respectively include a first barrier layer (922) and a first wiring layer (920A & 920B) on the first barrier layer (922),
wherein the first barrier layers (922, page 25 par 3 states, “Examples of barrier layers may include but are not limited to titanium (Ti)…”) include a first conductive material,
wherein the first wiring layers (920A & 920B) include a second conductive material (page 37 par 4 states, “…first metal layer 920A and the neighboring first metal layer 920B includes copper, cobalt, ruthenium, nickel, …”), different from the first conductive material (titanium).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Narkeviciute into the structure of Lane in view of Uzoh and Parekh since Narkeviciute teaches an interconnection structure.
The ordinary artisan would have been motivated to modify Narkeviciute in combination with Lane in view of Uzoh and Parekh in the above manner for the motivation of integrating a liner around the conductive wiring to also act as a diffusion barrier layer. Page 37 par 3 states, “The first barrier layer 922 may provide a diffusion barrier layer and/or liner layer”
Lane in view of Uzoh and Parekh and Narkeviciute does not explicitly teach the extension portion of the upper insulating structure contacts side surfaces of the first barrier layers and side surfaces of the first wiring layers.
Narkeviciute does teach the wiring portions include a first barrier layer (922) and a first wiring layer (920A & 920B) on the first barrier layer (922). Integrating Narkeviciute’s teachings of 920A/B and 922 into Lane for 42 and 44 will provide the extension portion (Lane, 62B, [0099], FIG. 7B) of the upper insulating structure (Lane, 30) contacts (mechanically) side surfaces of the first barrier layers and side surfaces of the first wiring layers (Narkeviciute 920A & 922 into Lane 42 & Narkeviciute 920B & 922 into Lane 44, Narkeviciute FIG. 9 & Lane FIG. 7B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Narkeviciute into the structure of Lane in view of Uzoh and Parekh and Narkeviciute.
The ordinary artisan would have been motivated to modify Narkeviciute in combination with Lane in view of Uzoh and Parekh and Narkeviciute in the above manner for the motivation of integrating a liner around the conductive wiring to also act as a diffusion barrier layer. Page 37 par 3 states, “The first barrier layer 922 may provide a diffusion barrier layer and/or liner layer”
Re Claim 16 Lane in view of Uzoh and Parekh and Narkeviciute teaches the semiconductor device of claim 15, wherein the second conductive material (Narkeviciute, 920A & 920B, page 37 last par) includes ruthenium (Ru).
Re Claim 17 Lane in view of Uzoh and Parekh and Narkeviciute teaches the semiconductor device of claim 15, further comprising:
an upper conductive structure (Narkeviciute, 960 and 962, page 39 par 2) electrically connected to at least one of the first wiring portion (920A) and the second wiring portion,
wherein the upper conductive structure (960 and 962) includes a second barrier layer (962) and a second wiring layer (960) on the second barrier layer (962),
wherein the second barrier layer (962) covers a side surface and a lower surface of the second wiring layer (960), and
wherein the second wiring layer (960) is spaced apart from the upper insulating structure (940, page 38 last par) by the second barrier layer (962, FIG. 9).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20230155001 A1) in view of Uzoh et al. (US 20200126861 A1, IDS) and Parekh (US 20210398847 A1).
Re Claim 19 Chen teaches a semiconductor device (FIG. 20) comprising:
a lower structure (FIG. 20 under 88A) including a substrate (20) [0012], a gate (66) [0024], an active region (36) [0016], a source/drain region (52) [0021], a lower insulating layer (82) [0033], and a contact plug (84) [0034];
a conductive wiring (120) [0053] on the lower structure (FIG. 20A under 88A);
an interlayer insulating layer (88B) [0037] on the lower structure (FIG. 20A under 88A) and on a side surface of the conductive wiring (120);
a protective insulating layer (102) on the interlayer insulating layer (88B) and the conductive wiring (120); and
wherein the active region (36) is on the substrate (20),
wherein the gate (66) is provided on the active region (36) and crosses the active region (36),
wherein the source/drain region (52) is on at least one side of the gate (66) and is disposed on the active region (36),
wherein the lower insulating layer (82) covers at least a portion of the source/drain region (52), and
wherein the contact plug (84) is on the source/drain region (52) and is electrically connected to the conductive wiring (120, FIG. 20A).
Chen does not teach an upper insulating structure including an upper interlayer portion on the protective insulating layer, and an extension portion extending from the upper interlayer portion, penetrating through the protective insulating layer, and extending into an interior of the lower structure,
Uzoh teaches an upper insulating structure (410) [0030] including an upper interlayer portion (FIG. 4G, 410 portions directly over 404) on the protective insulating layer (202) [0018], and an extension portion (410 that extends into 402, FIG. 4G) extending from the upper interlayer portion (410 directly over 404), penetrating through the protective insulating layer (202), and extending into an interior of the lower structure (402, [0027], FIG. 4G).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Uzoh into the structure of Chen since Uzoh teaches a structure with insulators penetrating metal layers.
The ordinary artisan would have been motivated to modify Uzoh in combination with Chen in the above manner for the motivation of optimally integrating an insulating layer through a metal layer to allow for an optimal structure to be handled during fabrication to minimize costs. [0003] states, “Thin wafer handling in 2.5D and 3D technologies adds cost and complexity in assembly. In particular, wafer bow and cracking of thin wafers, including the interposer, can cause great difficulty during assembly.”
Chen in view of Uzoh does not teach the extension portion penetrating through the conductive wiring.
Parekh teaches extension portion (260 between 256) [0087] penetrating through the conductive wiring (256, FIG. 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Parekh into the structure of Chen in view of Uzoh since Parekh teaches a semiconductor structure with insulators penetrating metal layers.
The ordinary artisan would have been motivated to modify Parekh in combination with Chen in view of Uzoh in the above manner for the motivation of optimally integrating an insulating layer through a metal layer to increase the level of integration of features within a microelectronic device. [0003] states, “Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features.”
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20230155001 A1) in view of Uzoh et al. (US 20200126861 A1, IDS) and Parekh (US 20210398847 A1) as applied to claim 19 above, and further in view of Lin et al. (US 20230268386 A1).
Re Claim 20 Chen in view of Uzoh and Parekh teaches the semiconductor device of claim 19, but does not teach:
a plurality of channel layers on the active region and spaced apart from each other to be surrounded by the gate.
Lin teaches a plurality of channel layers (31) [0067] on the active region (311 is in both the channel region in FIG. 22 and fins 401 [0024] in FIG. 2B) and spaced apart from each other to be surrounded by the gate (321) [0070].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Uzoh into the structure of Chen in view of Uzoh and Parekh since Lin teaches a gate all around structure.
The ordinary artisan would have been motivated to modify Lin in combination with Chen in view of Uzoh and Parekh in the above manner for the motivation of optimally integrating a gate around channel layers to build a device that is as small as possible and still functions at a peak level. [0001] states, “The semiconductor integrated circuit (IC) industry has, over the decades, experienced tremendous advancements and is still undergoing vigorous development. With dramatic advances in technology, the industry pays much attention on the development of small IC devices with high performance and low cost.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 7/20/26
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