DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/19/2025 have been fully considered but they are not persuasive.
Applicant argues on page 2-3 that claim 1 explicitly recites that an electrode layer that covers the surface layer of the semiconductor substrate and that the electrode layer further covers the upper side wall of the trench, as shown in figs. 7 and 8 of the instant application. Applicant specifically points to source contact 63 in the clearance gap 37 recessed portion 61 that extends beyond the insulating film 28 which forms the trench 12.
Examiner respectfully disagrees. The claim does not require “the insulating film 28 which forms the trench 12.” The claims merely requires the “electrode layer that covers the surface layer of the semiconductor substrate” and the electrode layer further covers the upper side wall of the trench.” Both of these limitations are taught by Okada in fig. 7B, where the trench is shown in fig. 6L, where the region that electrode 63 contact the sidewall of clearance gap 37 which is an extension of trench 12. Since these claim limitations are met, Examiner takes the position that each and every limitation of the claim are taught by Okada.
Applicant argues on page 3 that Okada inherently does not disclose an RC-IGBT and has not disclosure for diode areas.
Examiner respectfully disagrees. The claim does not require an RC-IGBT. The claim is to a method of manufacturing a semiconductor device and recites a diode trench gate. Fig. 7B shows a diode 39 as well as trench gate structures 29, therefore each and every limitation of the claim are taught by Okada.
Applicant further argues that a field plate trench 12 of Okada to the diode trench gate in the diode area of an RC-IGBT.
Examiner respectfully disagrees. this segment of the arguments does not specifically point out what claim limitations are not taught by Okada. The conclusory statements appears to treat Okada’s teachings as being applied to another references. It is reminded that Okada was used in an anticipation rejection under 102 and it is asserted that Okada teaches each and every limitation of claim 1. Consideration of the IE effect is immaterial to the method of manufacturing a device and the application of Okada to the claimed method of manufacturing. Anticipation of claim 1 by Okada is being maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okada et al. (US PGPub 2018/0114857; hereinafter “Okada”).
Re claim 1: Okada teaches (e.g. figs. 6F-6L and 7B) a method of manufacturing a semiconductor device, comprising the processes of: preparing a semiconductor substrate (substrate 2; e.g. paragraph 54) that includes a first semiconductor layer (40, 15) of a first conductivity type (p-type) provided as a surface layer (40, 15 is a surface layer and has a surface) on an upper surface side (upper surface side of 2) thereof, and a second semiconductor layer (upper layer portion of 2; hereinafter “2SL”) of a second conductivity type (n-type) provided below the first semiconductor layer (40, 15); forming a diode trench gate (34, 28, 29) that includes a diode trench insulation film (34, 28) and a diode trench electrode (29), the diode trench insulation film (34, 28) being formed on an inner wall of a trench (trench 12; e.g. paragraph 60) that extends from an upper surface (upper surface of 2) of the semiconductor substrate (2) through the first semiconductor layer (40, 15) to the second semiconductor layer (2SL), the diode trench electrode (29) being provided inside the trench (12); and forming an electrode layer (63) that covers the surface layer (40, 15) of the semiconductor substrate (2), wherein the diode trench insulation film (34, 28) is formed along, out of the inner wall (55 is a thermal oxide; e.g. paragraph 90) of the trench (12), a bottom and a lower side wall (bottom and bottom portion of side wall of 12) that is located below an upper side wall (upper portion of side wall of 12) located on an upper end side of the trench (12), the electrode layer (63) further covers the upper side wall (upper sidewall of 12 as shown in fig. 6L) of the trench (12), and the first semiconductor layer (40, 15) is in contact with the electrode layer (63) on the upper side wall of the trench (12).
Re claim 2: Okada teaches the method of manufacturing the semiconductor device, according to claim 1, wherein the process of forming the diode trench gate (34, 28, 29) includes: forming an insulation film (34, 28) on the inner wall of the trench (12 is formed with dielectrics 55 and 56 as shown in fig. 6C-F and dielectric 28 as shown in fig. 6H); forming the diode trench electrode (59 as shown in fig. 6H) inside the trench (12) via the insulation film (28); and after the formation of the diode trench electrode (29), etching (etching 28; e.g. paragraph 100) the insulation film (28) from the upper surface side of the semiconductor substrate (2) to expose the upper side wall of the trench (12).
Re claim 3: Okada teaches the method of manufacturing the semiconductor device, according to claim 2, wherein the process of forming the electrode layer (63) includes: depositing a material (63 as shown in fig. 7B) for the electrode layer on clearance between the diode trench electrode (29) and the upper side wall of the trench (12) formed by etching (paragraph 100) the insulation film (28).
Re claim 5: Okada teaches the method of manufacturing the semiconductor device, according to claim 2, wherein in the process of forming the diode trench insulation film (28), a selection ratio of an etch rate of the insulation film (28) and an etch rate of the first semiconductor layer (40, 15) is higher than or equal to 11.0 (the method and structure as substantially identical to those claimed, therefore claimed properties are presumed to be present, see MPEP 2112.01(ii)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okada as applied to claim 2 above, and further in view of Harada (US PGPub 2007/0267663).
Re claim 4: Okada teaches substantially the entire method as recited in claim 2 except explicitly teaching the method of manufacturing the semiconductor device, according to claim 2, wherein the electrode layer (63) is formed by CVD.
Harada teaches the known process of forming electrode films using a CVD process (see paragraph 42).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the CVD method for forming an electrode as taught by Harada in the method of Okada in order to have the predictable result of simplifying manufacture by using a known method capable of easily forming an electrode.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okada as applied to claim 2 above, and further in view of Kamibaba et al. (US PGPub 2018/0294258; hereinafter “Kamibaba”).
Re claim 6: Okada teaches the method of manufacturing the semiconductor device according to claim 2, wherein the insulation film (34, 28) is formed by dry etching (RIE; e.g. paragraph 100);
Okada is silent as to explicitly teaching the dry etching is conducted in a gas atmosphere containing fluorocarbon.
Kamibaba teaches (e.g. paragraph 77) the dry etching is conducted in a gas atmosphere containing fluorocarbon (RIE can utilize trifluoromethane or the like as the etching gas; e.g. paragraph 77).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the fluorocarbon gas for an RIE process as taught by Kamibaba in the method of Okada in order to have the predictable result of simplifying manufacture by using a known gas capable of etching.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898