DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/13/2026 has been entered.
Response to Arguments
Applicant's arguments filed 4/13/2026 have been fully considered but they are moot in view of the new grounds of rejection. The amendment broadened some aspects of the claims so that the prior art of record would still read on claim 1, however, claims 2-6 have been objected to allow.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okada et al. (US PGPub 2018/0114857; hereinafter “Okada”).
Re claim 1: Okada teaches (e.g. figs. 6F-6L and 7B) a method of manufacturing a semiconductor device, comprising the processes of: preparing a semiconductor substrate (substrate 2; e.g. paragraph 54) that includes a first semiconductor layer (40, 15) of a first conductivity type (p-type) provided as a surface layer (40, 15 is a surface layer and has a surface) on an upper surface side (upper surface side of 2) thereof, and a second semiconductor layer (upper layer portion of 2; hereinafter “2SL”) of a second conductivity type (n-type) provided below the first semiconductor layer (40, 15); forming a trench (contact hole 45; e.g. paragraph 100) including an inner wall (second surface 66; e.g. paragraph 79) that extends from an upper surface (upper surface of 2, 14; hereinafter “US”) of the semiconductor substrate (2) through the first semiconductor layer (40, 15) to the second semiconductor layer (2SL), the inner wall (66) being configured as an upper side wall (upper portion of 66; hereinafter “USW”) located on an upper end side of the trench (45), a lower side wall (lower portion of 66; hereinafter “LSW”) that is located below the upper side wall (USW), and a bottom (bottom of 66; hereinafter “B”); forming a diode trench gate (34, 28, 29) that includes a diode trench insulation film (34, 28) and a diode trench electrode (29), the diode trench insulation film (34, 28) being formed along the bottom (B) and the lower side wall (LSW), and the diode trench electrode (29) being provided inside the trench (45); and forming an electrode layer (63) that covers the surface layer (40, 15) of the semiconductor substrate (2), and further covers the upper side wall of the trench (45), the first semiconductor layer (40, 15) being in contact with the electrode layer (63) on the upper side wall (USW) of the trench (45).
Allowable Subject Matter
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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