CTNF 18/659,205 CTNF 99861 Detailed Action Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims The following is in response to the communication filed 5/9/2024 Claims 1-21 are currently pending. Claims 1-21 have been examined. Priority Applicant' s claim for the benefit of prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to French Patent Application No. 2304734, filed on May 12, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on 5/9/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: CONTACT WITH REDUCED EFFECTIVE CONTACT DIAMETER WITH A DIELECTRIC COATING LAYER FOR ELECTRONIC COMPONENT Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-3, 5-8, 10-16, 18, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lu et al. US 20230411457 A1 (hereinafter Lu) . Regarding claim 1 , Lu discloses: A method for manufacturing a contact on a semiconductor region of an electronic component, (Lu, Figs. 1-24B, intermediate stages of formation of a device) the method comprising: forming a coating layer of dielectric material (Fig. 24B, dielectric layer 80) , with a first thickness, (the material would by necessity have a thickness) on at least one side wall of an opening (Fig. 16B, trenches 78) crossing through a dielectric region (Fig. 19B, ILD 76, and capping layer 86) of the electronic component along a longitudinal direction from a first surface of the dielectric region, and opening out at the semiconductor region; (Fig. 16B, source/drain region 48) and forming a metal filler layer (Fig. 24B, filling metal 92) to fill the opening (trench 78) coated with the coating layer. (dielectric layer 80) Regarding claim 2, Lu further discloses: forming a silicide interface layer (Fig. 24B, silicide region 88) comprising an interface between the semiconductor region (Fig. 24B, source/drain region 48) and the contact; (Fig. 24B, filling metal 92) and after forming the silicide interface layer, (Fig 20B, [0045] forming the silicide region) forming the opening (trench 78) through the dielectric region (capping layer 86) , wherein a width of the silicide interface layer is greater than a diameter of the opening. (Fig. 20B shows that the silicide region 88 is wider than the diameter at the bottom of the trench 78.) Regarding claim 3, Lu further discloses: the opening has a fixed cross-section, and the first thickness is determined for adapting an effective cross-section of the contact by reducing the cross-section of the opening. (The effective cross-section of the metal filling 92 is less than the total thickness of the trench 78 by the inclusion of the dielectric layer and then capping layer 90.) Regarding claim 5, Lu further discloses: forming a diffusion barrier layer (capping layer 90) at a bottom of the opening and laterally in the opening on the coating layer, (Fig. 24B, the capping layer 90 is on the bottom of what was the trench 78 and on the sidewalls of the dielectric layer 80.) the formation of the diffusion barrier layer being carried out after forming the coating layer and before forming the filling layer. (Fig. 21B, so that the capping layer is formed after the dielectric layer 80 and before the filling metal layer 92.) Regarding claim 6, Lu further discloses: depositing a metal layer (Fig. 22B, filling metal 92) from the first surface of the dielectric region; (Fig. 22B, the filling metal is deposited over the ILD 76) and removing a portion of the metal layer extending over the openings and the first surface of the dielectric region to make the contact flush with the first surface. (Fig. 22B, the metal layer is flush with the top of the ILD layer.) Regarding claim 7, Lu further discloses: removing the portion of the metal layer comprises a chemical mechanical polishing. (Lu, [0047], metal layer is planarized using a CMP process.) Regarding claim 8, Lu further discloses: the dielectric material of the coating layer, or of the layer of dielectric material, is chosen from one or a plurality of materials among: silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, or silicon carbonitride; ([0042], dielectric layer 80 is made of silicon nitride.) and/or the metal of the filler layer, or of the metal layer, is chosen among tungsten or copper. ([0047], filling metal 92 is made of tungsten.) Regarding claim 10, Lu discloses: A method for manufacturing a contact on a semiconductor region of an electronic component, (Lu, Figs. 1-24B, intermediate stages of formation of a device) the method comprising: forming a coating layer of dielectric material (Fig. 24B, dielectric layer 80) , with a first thickness, (the material would by necessity have a thickness) on at least one side wall of an opening (Fig. 16B, trenches 78) crossing through a dielectric region (Fig. 19B, ILD 76, and capping layer 86) of the electronic component along a longitudinal direction from a first surface of the dielectric region, and opening out at the semiconductor region; (Fig. 16B, source/drain region 48) and forming a metal filler layer (Fig. 24B, filling metal 92) to fill the opening (trench 78) coated with the coating layer, (dielectric layer 80) wherein forming the coating layer comprises: depositing a layer of dielectric material (dielectric layer 80) from the first surface of the dielectric region, (Fig. 17B, dielectric material 80 is on the top of the ILD 76.) at least on the side walls and at a bottom of the opening; (Fig. 17B, the dielectric material 80 is on the sidewalls and bottom of the trench 78.) and removing by etching of a portion of the layer of dielectric material located at the bottom of the opening. (Fig. 18B, dielectric material 80 is removed from the bottom of the trench 78.) Regarding claim 11, Lu further discloses: forming a silicide interface layer (Fig. 24B, silicide region 88) comprising an interface between the semiconductor region (Fig. 24B, source/drain region 48) and the contact; (Fig. 24B, filling metal 92) and after forming the silicide interface layer, (Fig 20B, [0045] forming the silicide region) forming the opening (trench 78) through the dielectric region (capping layer 86) , wherein a width of the silicide interface layer is greater than a diameter of the opening. (Fig. 20B shows that the silicide region 88 is wider than the diameter at the bottom of the trench 78.) Regarding claim 12, Lu further discloses: the removing by etching further comprises removing a portion of the dielectric material layer located on the first surface of the dielectric region. ((Fig. 18B, dielectric material 80 is removed from the top of the ILD 76.) Regarding claim 13, Lu further discloses: the etching is an anisotropic plasma etching and etches the dielectric material layer along the longitudinal direction. (Fig. 18B, [0042], the dialectic layer 80 undergoes an anisotropic etch process to remove the horizontal portions. ) Regarding claim 14, Lu further discloses: the opening has a fixed cross-section, the method further comprising determining the first thickness for adapting an effective cross-section of the contact by reducing the cross-section of the opening. (The effective cross-section of the metal filling 92 is less than the total thickness of the trench 78 by the inclusion of the dielectric layer and then capping layer 90.) Regarding claim 15, Lu discloses: An electronic device (Fig. 24B, showing a GAA transistor device) comprising: an electronic component comprising at least one contact (filling metal 92, capping layer 90 and dielectric material 80) on a semiconductor region (source/drain regions 48) of the electronic component, each contact being positioned in an opening crossing through a dielectric region (filling metal 92 is openings through the ILD 76) of the electronic component along a longitudinal direction from a first surface of the dielectric region, (the ILD 76 separating in the filling metal 92 contacts in the longitudinal direction) and opening out at the semiconductor region, the contact (filling metal 92, capping layer 90, and dialectical material 80) comprising a coating layer of dielectric material, (dielectric material 80) with a first thickness, (dielectric material by necessity has a thickness) extending along at least one side wall of the opening and a filler layer of metal (filling metal 92) in the opening coated with the coating layer. (See Fig. 24B.) Regarding claim 16, Lu further discloses: further comprising a diffusion barrier layer (Fig. 24B, capping layer 90) at a bottom of the opening and laterally in the opening (See Fig. 24B, capping layer 90 is on the bottom of the opening and the sidewalls of the opening.) between the coating layer and the filler layer. (See Fig. 24B, capping layer 90 is between the dielectric layer 80 and filling metal 92.) Regarding claim 18, Lu further discloses: the dielectric material of the coating layer, or of the coating layer of dielectric material, is chosen from one or a plurality of materials among: silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, or silicon carbonitride; ([0042], dielectric layer 80 is made of silicon nitride.) and/or the metal of the filler layer, or of the metal layer, is chosen among tungsten or copper. [0047], filling metal 92 is made of tungsten.) Regarding claim 20, Lu further discloses: the electronic component comprises a silicide interface layer (Fig. 24B, silicide region 88) forming an interface between the semiconductor region (Fig. 24B, source/drain region 48) and the contact, (Fig. 24B, filling metal 92) wherein a width of the silicide interface layer is greater than a diameter of the opening. (Fig. 20B shows that the silicide region 88 is wider than the diameter at the bottom of the trench 78.) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-22-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim 1 above, and further in view of Al-Amoody et al. US 20220189818 A1 (hereinafter Al-Amoody) . Regarding claim 4, Lu discloses all the elements of claim 1. Lu further discloses: the first thickness (See annotated Fig. 24B below, the thickness of the dielectric material E1.) is determined for adapting the second diameter by reducing the first diameter by at least twice the first thickness. (The second diameter, D2, being the diameter of the filling metal layer is less than the first diameter, where the first diameter, D0, is the of trench without any layers within it. D2 = D0 – (2*E1) – (2*thickness of capping layer 90). PNG media_image1.png 836 545 media_image1.png Greyscale Lu does not specifically show the shape of the contact being a circular cylinder shape. However, Al-Amoody, which teaches contacts for integrated circuits, (Background/Summary) discloses: the opening has a circular (Al-Amoody, Fig. 2A, shows the top view of the contact being a circular shape.) cylinder (Fig. 1A, shows the side view which is would make the contact a cylinder.) shape with a first diameter (See annotated Fig. 2A, first diameter D0 being the total opening diameter.) , the contact having a circular cylinder shape of a second diameter (annotated Fig. 2A, second diameter D2 being the diameter of the metal material) smaller than the first diameter, PNG media_image2.png 482 511 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lu to have the opening has a circular cylinder shape with a first diameter, as taught by Al-Amoody for purposes of having a single continuous annular sidewall. (Al-Amoody, [0032].) 07-22-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim 1 above, and further in view of Kinoshita et al. US 6271087 B1 (hereinafter Kinoshita) and Najjar et. al. US 20180355502 A1 (hereinafter Najjar) . Regarding claim 9, Lu discloses all the elements of claim 1. Lu does teach a coating layer made of a dielectric material (Lu, Fig. 24B, dielectric layer 80) that would by necessity have a thickness. Lu also teaches an opening (Fig. 16B, trenches 78) which by necessity would have a width/diameter. Lu does not specifically disclose: the first thickness of the coating layer is greater than or equal to 50 nm, wherein the opening has a diameter in a range 225 to 275 nm. Kinoshita which teaches a semiconductor device and a method to makes contacts to the device (Kinoshita, Abstract) ,discloses: the first thickness of the coating layer (Fig. 4A, col. 8, lines 14-15 etch stop layer 231 made of a dielectric material that covers the semiconductor device.) is greater than or equal to 50 nm. (Col. 8, lines 23-27, the thickness is between 30-100nm.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lu to have the first thickness of the coating layer is greater than or equal to 50 nm as taught by Kinoshita in order to reduces the effective spacing in the horizontal direction between the multi-layer stacked gate structures. (Kinoshita, col. 6 lines 63-66.) Lu and Kinoshita do not appear to specifically disclose: wherein the opening has a diameter in a range 225 to 275 nm. Najjar, which teaches features related to vias used in integrated circuit devices. (Najjar, Abstract.) Najjar discloses that vias for three-dimensional integrated circuits such as RF devices, CMOS image sensors, memory device (Flash, DRAM, SRAM) as well as analog and logic devices could have entry dimensions including a diameter between 200 nm to 200 microns. (Najjar, [0004] – [0005].) One of ordinary skill in the art would consider the size of the contact in order to achieve a specific conductivity without using an excess of material for a specific device. If the contact area is too big it effects the size of the device but if the contacts are too small the conductivity would be negatively affected. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lu in view of Kinoshita, based on the teachings of Najjar, to have specific via parameters, as it has been recognized that diameter/width of the trench would be a result effective variable that would be optimized for a specific device at a specific technology node. See MPEP 2144.05 II.B It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990) . 07-22-aia AIA Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim 15 above, and further in view of Tsai et al. US 20170345706 A1 (hereinafter Tsai) . Regarding claim 17, Lu disclose all the elements of claim 15. Lu does not appear to disclose: an air cavity, crossing through an interconnection region of the electronic component and the dielectric region near the contact. Tsai, which teaches a semiconductor structure with a void extending within the dielectric material (Tsai, Abstract) , discloses: an air cavity, (Fig. 10, void 105) crossing through an interconnection region (region with the second dielectric layer 103c and the top of conductive structure 104) of the electronic component (semiconductor structure 200) and the dielectric region (first dielectric layer 103a) near the contact. (bottom conductive structure 104 within first dielectric layer 103a) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lu to have an air cavity, crossing through an interconnection region of the electronic component and the dielectric region near the contact as taught by Tsai for purposes of reducing signal leakage or cross talk by using air as a low k dielectric. (Tsai, [0014].) 07-22-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim 15 above, and further in view of Kinoshita . Regarding claim 19, Lu discloses all the elements of claim 15. Lu does teach a coating layer made of a dielectric material (Lu, Fig. 24B, dielectric layer 80) that would by necessity have a thickness. Lu does not appear to disclose: the first thickness of the coating layer is greater than or equal to 50 nm. Kinoshita which teaches a semiconductor device and a method to makes contacts to the device (Kinoshita, Abstract) ,discloses: the first thickness of the coating layer (Fig. 4A, col. 8, lines 14-15 etch stop layer 231 made of a dielectric material that covers the semiconductor device.) is greater than or equal to 50 nm. (Col. 8, lines 23-27, the thickness is between 30-100nm.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lu to have the first thickness of the coating layer is greater than or equal to 50 nm as taught by Kinoshita in order to reduces the effective spacing in the horizontal direction between the multi-layer stacked gate structures. (Kinoshita, col. 6 lines 63-66.) 07-22-aia AIA Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim s 1 and 15 above, and further in view of Najjar et. al. US 20180355502 A1 (hereinafter Najjar) Regarding claim 21, Lu discloses all the elements of claim 15. Lu teaches that there is an opening (Fig. 16B, trenches 78) which by necessity would have a width/diameter. Lu does not appear to specifically disclose: wherein the opening has a diameter between 225 nm and 275 nm. Najjar, which teaches features related to vias used in integrated circuit devices. (Najjar, Abstract.) Najjar discloses that vias for three-dimensional integrated circuits such as RF devices, CMOS image sensors, memory device (Flash, DRAM, SRAM) as well as analog and logic devices could have entry dimensions including a diameter between 200 nm to 200 microns. (Najjar, [0004] – [0005].) One of ordinary skill in the art would consider the size of the contact in order to achieve a specific conductivity without using an excess of material for a specific device. If the contact area is too big it effects the size of the device but if the contacts are too small the conductivity would be negatively affected. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lu, based on the teachings of Najjar, to have specific via parameters, as it has been recognized that diameter/width of the trench would be a result effective variable that would be optimized for a specific device at a specific technology node. See MPEP 2144.05 II.B It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). Prior Art Considered Pertinent 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chou et al. US 20210098365 A1 – Fig. 1L in which there is contact over a semiconductor region that has a contact spacer, barrier layer and conductive layer. Lai et al. US 8541303 B2 – Fig. 8 a silicide 118 is on source/drain that is greater than the width/diameter the contact structure 126 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HEIM KIRIN GREWAL/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/659,205 Page 2 Art Unit: 2812 Application/Control Number: 18/659,205 Page 3 Art Unit: 2812 Application/Control Number: 18/659,205 Page 4 Art Unit: 2812 Application/Control Number: 18/659,205 Page 5 Art Unit: 2812 Application/Control Number: 18/659,205 Page 6 Art Unit: 2812 Application/Control Number: 18/659,205 Page 7 Art Unit: 2812 Application/Control Number: 18/659,205 Page 8 Art Unit: 2812 Application/Control Number: 18/659,205 Page 9 Art Unit: 2812 Application/Control Number: 18/659,205 Page 10 Art Unit: 2812 Application/Control Number: 18/659,205 Page 11 Art Unit: 2812 Application/Control Number: 18/659,205 Page 12 Art Unit: 2812 Application/Control Number: 18/659,205 Page 13 Art Unit: 2812 Application/Control Number: 18/659,205 Page 14 Art Unit: 2812 Application/Control Number: 18/659,205 Page 15 Art Unit: 2812
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