Attorney’s Docket Number: 10-2023-0167066
Filing Date: 05/09/2024
Claimed Priority Date: 11/27/2023 (KR10-2023-0167066)
Applicants: Choi
Examiner: Aneesa Baig
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14-16 are rejected under 35 U.S.C. 102 (a)(1) as anticipated by Ryu et al (US 20220223732 A1, Hereinafter Ryu).
Regarding Claim 14, Ryu (e.g., Figure 1-10 [0015]-[0021][0047]) shows all aspects of the instant invention, including, a semiconductor device comprising:
a bit line extending in a first horizontal direction (120 extending in X direction);
a mold structure on the bit line and extending in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction (first interlayer insulating layer 112 extending in Y direction, Fig 2);
channel structures including horizontal portions in contact with an upper surface of the bit line and vertical channel portions extending upwardly from one ends of the horizontal portions (channel layer 130, including 132 and 134 extends in Z direction and in X direction);
a gate electrode on the channel structures (150A/B); and
landing pad structures on the vertical channel portions and electrically connected to the channel structures (landing pads 160A and 160B), wherein
the mold structure includes first portions and second portions alternately disposed in the second horizontal direction (mold structure includes a body and protrusions alternately disposed),
lower surfaces of the first portions of the mold structure have a first horizontal width in the first horizontal direction (See annotated image),
lower surfaces of the second portions of the mold structure have a second horizontal width in the first horizontal direction (See annotated image),
the second width is different from the first horizontal width (See annotated image),
the vertical channel portions are spaced apart from each other in the second horizontal direction (Fig 1 shows 130 spaced apart in Y direction), and
the vertical channel portions contact a side surface of the mold structure (Fig 2).
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Regarding Claim 15, Ryu shows he second horizontal width is greater than the first horizontal width, and the vertical channel portions respectively surround side surfaces of the second portions of the mold structure (See Fig 1 annotated above).
Regarding Claim 16, Ryu shows the vertical channel portions contacting side surface of the mold structure with the W1 width.
Allowable Subject Matter
Claims 17,18,19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-13 and 20 are allowable.
Regarding Claim 1, the closest identified prior art, Ryu, shows most aspects of the invention as disclosed above, and while Ryu shows a protrusion of the mold layer, it fails to anticipate or make obvious the following:
at least a portion of the vertical channel portion overlaps the mold structure in a second horizontal direction
Regarding Claim 20, the closest identified prior art, Ryu, shows most aspects of the invention as follows:
A semiconductor device comprising:
a lower structure including a circuit element (Fig 6 shows PT);
a bit line on the lower structure and extending in a first horizontal direction (120);
a mold structure on the bit line and extending in a second horizontal direction, intersecting the first horizontal direction (112);
channel structures including horizontal portions in contact with an upper surface of the bit line and vertical channel portions extending upwardly from one ends of the horizontal portions; a gate electrode on the channel structures (130);
a dielectric structure extending between the channel structures and the gate electrode in the second horizontal direction (gate insulating layer 140B );
an upper capping layer covering the mold structure and the upper insulating structure (116);
landing pad structures penetrating through the upper capping layer and electrically connecting to the channel structures (160); and
an upper insulating structure (114) spaced apart from the mold structure and covering the gate electrode and the bit line (114 covers the electrode 150 and covers the area above the bitline 120);
an information storage structure on the landing pad structures ([0060] ) , wherein
the vertical channel portions contact a side surface of the mold structure (Fig 2), and
However, Ryu fails to anticipate or make obvious the following:
at least a portion of the vertical channel portions overlaps the mold structure in the second horizontal direction.
Other prior art made of record (US 20230354605 A1, US 20250142908 A1) do show protrusions in the mold structure, however they do not show the channel portions overlapping with the mold in the second horizontal direction. Therefore, the above limitations in the entirety of their respective claims are neither anticipated nor rendered obvious over the prior art of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cite stacked multichip packages.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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